Datasheet

SN75DP139

SLLS977D –APRIL 2009–REVISED JULY 2013

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EXAMPLE – READING FROM THE SN75DP139:

The read operation consists of several steps. The I

C master begins the communication with the transmission of

the start sequence followed by the slave address of the SN75DP139 and logic address of 00h. The SN75DP139

will acknowledge it’s presence to the master and begin to transmit the contents of the memory registers. After

each byte is transferred the SN75DP139 will wait for either an acknowledge (ACK) or a not-acknowledge (NACK)

from the master. If an ACK is received the next byte of data will be transmitted. If a NACK is received the data

transmission sequence is expected to end and the master should send the stop command.

The SN75DP139 will continue to send data as long as the master continues to acknowledge each byte

transmission. If an ACK is received after the transmission of byte 0x0F the SN75DP139 will transmit byte 0x10

and continue to transmit byte 0x10 for all further ACK’s until a NACK is received.

The SN75DP139 also supports an accelerated read mode where steps 1–6 can be skipped.

SN75DP139 Read Phase

Step 1 0

C Start (Master) S

Step 2 7 6 5 4 3 2 1 0

C General Address Write (Master) 1 0 0 0 0 0 0 0

Step 3 9

C Acknowledge (Slave) A

Step 4 7 6 5 4 3 2 1 0

C Logic Address (Master) 0 0 0 0 0 0 0 0

Step 5 9

C Acknowledge (Slave) A

Step 6 0

C Stop (Master) P

Step 7 0

C Start (Master) S

Step 8 7 6 5 4 3 2 1 0

C General Address Read (Master) 1 0 0 0 0 0 0 1

Step 9 9

C Acknowledge (Slave) A

Step 10 7 6 5 4 3 2 1 0

C Read Data (Slave) Data Data Data Data Data Data Data Data

Where Data is determined by the Logic values Contained in the Sink Port Register

Step 11 9

C Not-Acknowledge (Master) X

Product Folder Links: SN75DP139