Datasheet

SN75DP139

www.ti.com

SLLS977D –APRIL 2009–REVISED JULY 2013

Figure 29. I

C Read Cycle

Figure 30. Multiple Byte Read Transfer

SLAVE ADDRESS

Both SDA and SCL must be connected to a positive supply voltage via a pull-up resistor. These resistors should

comply with the I

C specification that ranges from 2kΩ to 19kΩ. When the bus is free, both lines are high. The

address byte is the first byte received following the START condition from the master device. The 7 bit address is

factory preset to 1000000. Table 2 lists the calls that the SN75DP139 will respond to.

Table 2. SN75DP139 Slave Address

Fixed Address Read/Write Bit

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

(MSB) (R/W)

1 0 0 0 0 0 0 1

Sink Port Selection Register and Source Plug-In Status Register Description (Sub-Address)

The SN75DP139 operates using a multiple byte transfer protocol similar to Figure 30. The internal memory of the

SN75DP139 contains the phrase “DP-HDMI ADAPTOR<EOT>” converted to ASCII characters. The internal

memory address registers and the value of each can be found in Table 3.

During a read cycle, the SN75DP139 will send the data in its selected sub-address in a single transfer to the

master device requesting the information. See the Example – Reading from the SN75DP139 section of this

document for the proper procedure on reading from the SN75DP139.

Table 3. SN75DP139 Sink Port and Source Plug-In Status Registers Selection

Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10

Data 44 50 2D 48 44 4D 49 20 41 44 41 50 54 4F 52 04 FF

Product Folder Links: SN75DP139