Datasheet

SDA
SCL
Start
Condition
Stop
Condition
SDA
SCL
SN75DP139
www.ti.com SLLS977D –APRIL 2009–REVISED JULY 2013
APPLICATION INFORMATION
DVI APPLICATION
In DVI application case, it is recommended that between the SN75DP139 TMDS outputs (OUT_Dx) and a
through hole DVI connector a series resistor placeholder is incorporated. This could help in case if there are
signal integrity issues as well as help pass system level compliance.
I
2
C INTERFACE NOTES
The I2C interface can be used to access the internal memory of the SN75DP139. I
2
C is a two-wire serial
interface developed by Philips Semiconductor (see I
2
C-Bus Specification, Version 2.1, January 2000). The bus
consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and
SCL lines are pulled high. All the I
2
C compatible devices connect to the I
2
C bus through open drain I/O pins,
SDA and SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The
master is responsible for generating the SCL signal and device addresses. The master also generates specific
conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on
the bus under control of the master device. The SN75DP139 works as a slave and supports the standard mode
transfer (100 kbps) as defined in the I
2
C-Bus Specification.
The basic I2C start and stop access cycles are shown in Figure 25.
The basic access cycle consists of the following:
• A start condition
• A slave address cycle
• Any number of data cycles
• A stop condition
Figure 25. I
2
C Start and Stop Conditions
GENERAL I
2
C PROTOCOL
• The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 27. All I
2
C-compatible devices should
recognize a start condition.
• The master then generates the SCL pulses and transmits the 7-bit address and the read/write direction bit
R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition
requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 26). All devices
recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave
device with a matching address generates an acknowledge (see Figure 27) by pulling the SDA line low during
the entire high period of the ninth SCL cycle. On detecting this acknowledge, the master knows that a
communication link with a slave has been established.
• The master generates further SCL cycles to either transmit data to the slave (R/W bit 0) or receive data from
the slave (R/W bit 1). In either case, the receiver needs to acknowledge the data sent by the transmitter. So
an acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long
as necessary (See Figure 28 ).
• To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low
to high while the SCL line is high (see Figure 28). This releases the bus and stops the communication link
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