Datasheet
SN75DP139
SLLS977D –APRIL 2009–REVISED JULY 2013
www.ti.com
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
OH
Single-ended HIGH level output voltage AVCC = 3.3 V, R
T
= 50 Ω, AVCC–10 AVCC+10 mV
V
OL
Single-ended LOW level output voltage AVCC–600 AVCC-400 mV
V
SWING
Single-ended output voltage swing 400 600 mV
V
OC(SS)
Change in steady-state common-mode –5 5 mV
output voltage between logic states
V
OD(PP)
Peak-to-Peak output differential voltage 800 1200 mV
V
(O)SBY
Single-ended standby output voltage AVCC = 3.3 V, R
T
= 50 Ω, OE_N = AVCC–10 AVCC+10 mV
High
I
(O)OFF
Single-ended power down output 0V ≤ VCC ≤ 1.5 V, AVCC = 3.3 V, –10 10 μA
current R
T
= 50Ω
I
OS
Short circuit output current See Figure 19 –15 15 mA
R
INT
Input termination impedance 40 50 60 Ω
V
term
Input termination voltage 1 2 V
SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
PLH
Propagation delay time 250 350 600 ps
t
PHL
Propagation delay time 250 350 600 ps
t
R1
Rise Time (I2C_EN = HI, SRC = Hi-Z) 60 85 120 ps
t
F1
Fall Time (I2C_EN = HI, SRC = Hi-Z) 60 85 120 ps
t
R2
Rise Time (I2C_EN = Low, SRC = Hi-Z) 115 150 ps
t
F2
Fall Time (I2C_EN = Low, SRC = Hi-Z) 115 150 ps
t
R3
Rise Time (I2C_EN = HI, SRC = HI) 150 180 ps
t
F3
Fall Time (I2C_EN = HI, SRC = HI) 150 180 ps
AVCC=3.3 V, R
T
= 50 Ω, f = 1MHz,
t
R4
Rise Time (I2C_EN = HI, SRC = Low) 115 150 ps
R
Vsadj
= 4.02 kΩ
t
F4
Fall Time (I2C_EN = HI, SRC = Low) 115 150 ps
t
R5
Rise Time (I2C_EN = Low, SRC = HI) 175 220 ps
t
F5
Fall Time (I2C_EN = Low, SRC = HI) 175 220 ps
t
R6
Rise Time (I2C_EN = Low, SRC = Low) 150 180 ps
t
F6
Fall Time (I2C_EN = Low, SRC = Low) 150 180 ps
t
SK(P)
Pulse skew 8 15 ps
t
SK(D)
Intra-pair skew 20 65 ps
t
SK(O)
Inter-pair skew 20 100 ps
t
JITD(PP)
Peak-to-peak output residual data jitter AVCC = 3.3 V, R
T
= 50Ω, dR = 3Gbps, 14 50 ps
TMDS output slew rate (default).
R
Vsadj
= 4.02 kΩ (refer to Figure 18)
t
JITC(PP)
Peak-to-peak output residual clock jitter AVCC = 3.3 V, R
T
= 50Ω, f = 300 MHz 8 30 ps
TMDS output slew rate (default).
R
Vsadj
= 4.02 kΩ (refer to Figure 18)
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