Datasheet

Input
SCL_SOURCE
Output
SDA_SOURCE
t
PLH1
3.3V
V
OL
1.6V
SCL_SINK
SDA_SINK
5V
Input
20%
80%
SCL_SOURCE
Output
SDA_SOURCE
t
f1
t
PHL1
3.3V
1.6V
0.1V
5V
1.6V
V
OL
SCL_SINK
SDA_SINK
Input
20%
80%
SCL_SOURCE
Output
SCL_SINK
SDA_SINK
SDA_SOURCE
t
f2
t
PHL2
t
PLH2
5V
1.6V
0.1V
3.3V
1.6V
V
OL
SN75DP139
www.ti.com SLLS977D –APRIL 2009–REVISED JULY 2013
Figure 12. Source Side Output AC Measurements
Figure 13. Sink Side Output AC Measurements
Figure 14. Sink Side Output AC Measurements Continued
TMDS and Main link pins
The main link inputs are designed to support DisplayPort 1.1 specification. The TMDS outputs of the
SN75DP139 are designed to support the Digital Video Interface (DVI) 1.0 and High Definition Multimedia
Interface (HDMI) 1.4b specifications. The differential output voltage swing can be fine tuned with the R
Vsadj
resistor.
The DP++ (dual-mode) input of the SN75DP139 is designed to accommodate the standard DP level ac coupled
signal with no pre-emphasis with up to 16 inches of trace (4 mil 100 Ω differential stripline).
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