Datasheet

PULSE
GENERATOR
D.U.T.
R
T
V
OUT
V
CC
5V
R =2k
L
W
C =400pF
L
V
IN
PULSE
GENERATOR
D.U.T.
R
T
V
OUT
V
CC
3.3V
R =2k
L
W
C =100pF
L
V
IN
SN75DP139
SLLS977D –APRIL 2009–REVISED JULY 2013 www.ti.com
SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
PLH1
Propagation delay time, low to high Source to Sink 204 600 ns
t
PHL1
Propagation delay time, high to low Source to Sink 35 200 ns
t
PLH2
Propagation delay time, low to high Sink to Source 80 251 ns
t
PHL2
Propagation delay time, high to low Sink to Source 35 200 ns
t
f1
Output signal fall time Sink Side 20 72 ns
t
f2
Output signal fall time Source Side 20 72 ns
f
SCL
SCL clock frequency for internal register Source Side 100 kHz
t
W(L)
Clock LOW period for I
2
C register Source Side 4.7 μs
t
W(H)
Clock HIGH period for internal register Source Side 4.0 μs
t
SU1
Internal register setup time, SDA to SCL Source Side 250 ns
t
h(1)
Internal register hold time, SCL to SDA Source Side 0 μs
T
(buf)
Internal register bus free time between STOP and START Source Side 4.7 μs
t
su(2)
Internal register setup time, SCL to START Source Side 4.7 μs
t
h(2)
Internal register hold time, START to SCL Source Side 4.0 μs
t
su(3)
Internal register hold time, SCL to STOP Source Side 4.0 μs
Figure 10. Source Side Test Circuit (SCL_SOURCE, SDA_SOURCE)
Figure 11. Sink Side Test Circuit (SCL_SINK,SDA_SINK)
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