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SN75DP139

www.ti.com

SLLS977D –APRIL 2009–REVISED JULY 2013

DisplayPort to TMDS Level Shifting Re-driver

Check for Samples: SN75DP139

FEATURES

• DisplayPort Physical Layer Input Port to TMDS • Enhanced ESD: 10kV on All Pins

Physical Layer Output Port

• Enhanced Commercial Temperature Range:

• Integrated TMDS Level Shifting Re-driver With 0°C to 85°C

Receiver Equalization

• 48 Pin 7 × 7 QFN (RGZ) Package

• Supports Data Rates up to 3.4Gbps

• 40 Pin 5 x 5 QFN (RSB) Package

• Achieves HDMI 1.4b Compliance

APPLICATIONS

• 3D HDMI Support With TMDS Clock Rates up

to 340MHz

• Personal Computer Market

• 4k x 2k Operation (30Hz, 24bpp)

– DP/TMDS Dongle

• Deep Color Supporting 36bpp

– Desktop PC

• Integrated I

C Logic Block for DVI/HDMI

– Notebook PC

Connector Recognition

– Docking Station

• Integrated Active I

C Buffer

– Standalone Video Card

DESCRIPTION

The SN75DP139 is a Dual-Mode DisplayPort input to Transition-Minimized Differential Signaling (TMDS) output.

The TMDS output has a built in level shifting re-driver supporting Digital Video Interface (DVI) 1.0 and High

Definition Multimedia Interface (HDMI) 1.4b standards. The SN75DP139 is specified up to a maximum data rate

of 3.4Gbps, supporting resolutions greater then 1920x1200 or HDTV 12 bit color depth at 1080p (progressive

scan). SN75DP139 is compliant with the HDMI 1.4b specifications and supports optional protocol enhancements

such as 3D graphics at resolutions demanding a pixel rate up to 340MHz.

An integrated Active I

C buffer isolates the capacitive loading of the source system from that of the sink and

interconnecting cable. This isolation improves overall signal integrity of the system and allows for considerable

design margin within the source system for DVI / HDMI compliance testing.

A logic block was designed into the SN75DP139 in order to assist with TMDS connector identification. Through

the use of the I

C_EN pin, this logic block can be enabled to indicate the translated port is an HDMI port;

therefore legally supporting HDMI content.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (39 pages)

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SN75DP139 www.ti.com SLLS977D – APRIL 2009 – REVISED JULY 2013 DisplayPort to TMDS Level Shifting Re-driver Check for Samples: SN75DP139 FEATURES 1 • • • • • • • • • DisplayPort Physical Layer Input Port to TMDS Physical Layer Output Port Integrated TMDS Level Shifting Re-driver With Receiver Equalization Supports Data Rates up to 3.4Gbps Achieves HDMI 1.
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SN75DP139 SLLS977D – APRIL 2009 – REVISED JULY 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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SN75DP139 www.ti.
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SN75DP139 SLLS977D – APRIL 2009 – REVISED JULY 2013 www.ti.
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SN75DP139 www.ti.
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SN75DP139 SLLS977D – APRIL 2009 – REVISED JULY 2013 www.ti.com PIN FUNCTIONS PIN SIGNAL NO.
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SN75DP139 www.ti.com SLLS977D – APRIL 2009 – REVISED JULY 2013 Input/Output Equivalent Circuits VTERM VCC VTERM 50 W 50 W – + Figure 1. DisplayPort Input Stage Y Z 10 mA Figure 2.
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SN75DP139 SLLS977D – APRIL 2009 – REVISED JULY 2013 www.ti.com OE_N 2 I C_EN HPDINV SRC OVS DDC_EN HPD_SINK Figure 3. HPD and Control Input Stage VCC HPD_OUT Figure 4. HPD Output Stage SCL SDA AUX+/– 400 W VOL Figure 5.
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SN75DP139 www.ti.com SLLS977D – APRIL 2009 – REVISED JULY 2013 Table 1. Control Pin Lookup Table SIGNAL OE_N I2C_EN VSadj HPDINV SRC OVS DDC_EN (1) LEVEL (1) STATE DESCRIPTION H Power Saving Mode Main Link is disabled. IN_Dx termination = 50 Ω with common mode voltage set to 0V. OUT_Dx outputs = high impedance L Normal Mode IN_Dx termination = 50 Ω OUT_Dx outputs = active H HDMI L DVI 4.
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SN75DP139 SLLS977D – APRIL 2009 – REVISED JULY 2013 www.ti.com ORDERING INFORMATION (1) (1) PART NUMBER PART MARKING PACKAGE SN75DP139RGZR DP139 48-pin QFN Reel (large) SN75DP139RGZT DP139 48-pin QFN Reel (small) SN75DP139RSBR DP139 40-pin QFN Reel (large) SN75DP139RSBT DP139 40-pin QFN Reel (small) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com.
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SN75DP139 www.ti.com SLLS977D – APRIL 2009 – REVISED JULY 2013 THERMAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP θJB Junction-to-board thermal resistance RGZ package 10.9 RSB package 10.8 θJCT Junction-to-case-top thermal resistance RGZ package 22.5 RSB package 24.4 ψJB Junction-to-board thermal resistance metric High-K board (2) RGZ package 10.9 RSB package 10.
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SN75DP139 SLLS977D – APRIL 2009 – REVISED JULY 2013 www.ti.com RECOMMENDED OPERATING CONDITIONS (continued) over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT AUXILIARY AND I2C PINS VI Input voltage dR(I2C) I2C data rate SDA_SINK, SCL_SINK 0 SDA_SOURCE, SCL_SOURCE 5.5 3.6 V 100 kHz HPD_SINK, HPDINV, OE_N VIH High-level input voltage 2 5.5 V VIL Low-level input voltage 0 0.8 V VIH High-level input voltage 2 3.
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SN75DP139 www.ti.com SLLS977D – APRIL 2009 – REVISED JULY 2013 HPD_SINK HPDINV OE_N DDC_EN IN_Dx OUT_Dx DDC HPD_SOURCE MODE Input = H or L H H L 50 Ω termination active: Terminations connected to common Mode Voltage = 0V. Highimpedance Highimpedance Output = inverted, follows HPD_SINK Low Power Input = H or L H H H 50 Ω termination active: Terminations connected to common Mode Voltage = 0V.
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SN75DP139 SLLS977D – APRIL 2009 – REVISED JULY 2013 www.ti.com SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER tPD(HPD) TEST CONDITIONS Propagation delay MIN VCC = 3.6 V TYP 2 MAX 30 UNIT ns 1.1 V HPD Input/HPD_sink Dp139 HPD Output/HPD_source DP139 130 kW 100 kW 130 kW 10 kW HPD Input/HPD_sink 100 kW HPD Output/HPD_source 130 kW Pull down resistor on the sink side is integrated 130 kW Pull down resistor is integrated Figure 6.
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SN75DP139 www.ti.com SLLS977D – APRIL 2009 – REVISED JULY 2013 AUX / I2C pins The SN75DP139 utilizes an active I2C repeater. The repeater is designed to isolate the parasitic effects of the system in order to aid with system level compliance. In addition to the I2C repeater, the SN75DP139 also supports the connector detection I2C register. This register is enabled via the I2C_EN pin. When active an internal memory register is readable via the AUX_I2C I/O.
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SN75DP139 SLLS977D – APRIL 2009 – REVISED JULY 2013 www.ti.
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SN75DP139 www.ti.com SLLS977D – APRIL 2009 – REVISED JULY 2013 5V SCL_SINK SDA_SINK Input 1.6 V 0.1 V tPHL2 tPLH2 3.3 V 80% SCL_SOURCE SDA_SOURCE Output 1.6 V 20% VOL tf2 Figure 12. Source Side Output AC Measurements 3.3 V SCL_SOURCE SDA_SOURCE Input 1.6 V 0.1 V tPHL1 5V 80% SCL_SINK SDA_SINK Output 1.6 V 20% VOL tf1 Figure 13. Sink Side Output AC Measurements 3.3 V SCL_SOURCE SDA_SOURCE Input VOL tPLH1 SCL_SINK SDA_SINK Output 5V 1.6 V Figure 14.
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SN75DP139 SLLS977D – APRIL 2009 – REVISED JULY 2013 www.ti.com ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN AVCC = 3.
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SN75DP139 www.ti.com SLLS977D – APRIL 2009 – REVISED JULY 2013 VTERM 3.3V 50 Ω 50 Ω 50 Ω 50 Ω 0.5 pF D+ VD+ Receiver VID DV D- Y Driver VY Z VOD = VY - VZ VOC = (VY + VZ) VID = VD+ - VDVICM = (VD+ + VD-) 2 VZ 2 Figure 15. TMDS Main Link Test Circuit 2.2 V VTERM VID 1.8 V VID+ VID(pp) 0V tPHL 80% 0V 20% tf VID- tPLH 80% VOD(pp) VOD 20% tr Figure 16. TMDS Main Link Timing Measurements VOC ΔVOC (SS) Figure 17.
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SN75DP139 SLLS977D – APRIL 2009 – REVISED JULY 2013 www.ti.com Avcc (4) (8) RT Data + Parallel BERT Data - Coax Coax SMA Clk - RX +EQ SMA 600, 800 mV VPP Differential [No Pre-emphasis] Clk + SMA (1) FR 4 PCB trace & AC coupling Caps Coax Coax SMA SN 75 DP 139 Coax Coax FR 4 PCB trace AVcc RT SMA RX +EQ TTP 2 Jitter Test Instrument (2,3) RT Coax OUT SMA Coax (6) (7) TTP 1 (5) OUT SMA SMA RT Jitter Test Instrument (2,3) TTP 4 TTP 3 1.
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SN75DP139 www.ti.com SLLS977D – APRIL 2009 – REVISED JULY 2013 TYPICAL CHARACTERISTICS AVCC = 3.3 V, RT = 50Ω POWER DISSIPATION vs DATA RATE RESIDUAL JITTER OF 3Gbps vs SUPPLY VOLTAGE 50 420 45 Peak-to-Peak Residual Data Jitter (ps) 430 410 Power (mW) 400 0C 0C Slowest Edge Rate 390 25C 25C Slowest Edge Rate 380 85C 85C Slowest Edge Rate 370 360 40 35 0C 0C Slowest Edge Rate 30 25C 25C Slowest Edge Rate 85C 25 85C Slowest Edge Rate 20 15 350 340 10 0.5 1.0 1.5 2.0 2.
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SN75DP139 SLLS977D – APRIL 2009 – REVISED JULY 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) AVCC = 3.3 V, RT = 50Ω VOD vs Vsadj 1300 VCC = 3.0V VCC = 3.3V 1200 Differential Output Voltage (mV) VCC = 3.6V 1100 1000 900 800 700 600 3.5 4.0 4.5 5.0 5.5 6.0 6.5 VSadj Resistance (k C005 Figure 24.
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SN75DP139 www.ti.com SLLS977D – APRIL 2009 – REVISED JULY 2013 APPLICATION INFORMATION DVI APPLICATION In DVI application case, it is recommended that between the SN75DP139 TMDS outputs (OUT_Dx) and a through hole DVI connector a series resistor placeholder is incorporated. This could help in case if there are signal integrity issues as well as help pass system level compliance. I2C INTERFACE NOTES The I2C interface can be used to access the internal memory of the SN75DP139.
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SN75DP139 SLLS977D – APRIL 2009 – REVISED JULY 2013 www.ti.com with the addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of a stop condition, all devices know that the bus is released, and they wait for a start condition followed by a matching address. SDA SCL Data Line Stable; Data Valid Change of Data Allowed Figure 26.
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SN75DP139 www.ti.com SLLS977D – APRIL 2009 – REVISED JULY 2013 Figure 29. I2C Read Cycle Figure 30. Multiple Byte Read Transfer SLAVE ADDRESS Both SDA and SCL must be connected to a positive supply voltage via a pull-up resistor. These resistors should comply with the I2C specification that ranges from 2kΩ to 19kΩ. When the bus is free, both lines are high. The address byte is the first byte received following the START condition from the master device. The 7 bit address is factory preset to 1000000.
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SN75DP139 SLLS977D – APRIL 2009 – REVISED JULY 2013 www.ti.com EXAMPLE – READING FROM THE SN75DP139: The read operation consists of several steps. The I2C master begins the communication with the transmission of the start sequence followed by the slave address of the SN75DP139 and logic address of 00h. The SN75DP139 will acknowledge it’s presence to the master and begin to transmit the contents of the memory registers.
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SN75DP139 www.ti.com SLLS977D – APRIL 2009 – REVISED JULY 2013 Where X is an A (Acknowledge) or A (Not-Acknowledge) An A causes the pointer to increment and step 10 is repeated. An A causes the slave to stop transmitting and proceeds to step 12.
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SN75DP139 SLLS977D – APRIL 2009 – REVISED JULY 2013 www.ti.com REVISION HISTORY Changes from Revision A (July 2010) to Revision B Page • Added to FEATURES "40 Pin 5 x 5 QFN (RSB) Package" .................................................................................................. 1 • Changed OUT_Dx terminal connections .............................................................................................................................. 3 • Added RSB package drawing ...................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 23-Jul-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN75DP139RGZR VQFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 SN75DP139RGZR VQFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 SN75DP139RGZT VQFN RGZ 48 250 180.0 16.4 7.3 7.3 1.5 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN75DP139RGZR VQFN RGZ 48 2500 367.0 367.0 38.0 SN75DP139RGZR VQFN RGZ 48 2500 367.0 367.0 38.0 SN75DP139RGZT VQFN RGZ 48 250 210.0 185.0 35.0 SN75DP139RSBR WQFN RSB 40 3000 367.0 367.0 35.0 SN75DP139RSBT WQFN RSB 40 250 210.0 185.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.