Datasheet

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PIN CONFIGURATION
1
I
2
C_EN
VDD
ML_IN0(p)
HPD_OUT
SDA
VSadj
VCC
TMDS_2(n)
SCL
2 3 4 5 6 7 8
11
10
12
13
14
15
16
17
35
36
34
33
32
31
30
29
2627 24 23 22 21 2025
9
18
19
28
GND
VCC
LP
TMDS_2(p)
ML_IN0(n)
ML_IN1(p)
ML_IN1(n)
VCC
ML_IN2(p)
ML_IN2(n)
GND
ML_IN3(p)
ML_IN3(n)
VCC
GND
HPD_IN
GND
TMDS_CLK(n)
TMDS_CLK(p)
VCC
TMDS_0(n)
TMDS_0(p)
GND
TMDS_1(n)
TMDS_1(p)
SN75DP129
RHHPACKAGE
(TopView)
AUX_I
2
C(p)
1
AUX_I
2
C(n)
1
SN75DP129
SLAS583A JANUARY 2008 REVISED MARCH 2008
(1) I
2
C bus data (n-SDA) and clock (p-SCL) lines.
TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTION TYPE
NAME NO.
(1)
AUX_I
2
C
(2)
11(p), 12(n) I/O Source Side Bidirectional DisplayPort Auxiliary Data Line DDC LINK (Source)
GND 6, 10, 19, 25, 36 Ground Ground
HPD_IN 15 I Hot Plug Detect (HPD) Input Hot Plug Detect
HPD_OUT 13 O Hot Plug Detect (HPD) Output Hot Plug Detect
Internal I
2
C register enable, used for HDMI / DVI connector
I
2
C_EN 32 I Control
differentiation
LP 33 I Low Power Select Bar Control
ML_IN 0 34(p), 35(n) I DisplayPort Main Link Channel 0 Differential Input Main Link Input Pins
ML_IN 1 1(p), 2(n) I DisplayPort Main Link Channel 1 Differential Input Main Link Input Pins
ML_IN 2 4(p), 5(n) I DisplayPort Main Link Channel 2 Differential Input Main Link Input Pins
ML_IN 3 7(p), 8(n) I DisplayPort Main Link Channel 3 Differential Input Main Link Input Pins
TMDS_2 30(p), 29(n) O TMDS Data 2 Differential Output Main Link Output
TMDS_1 27(p), 26(n) O TMDS Data 1 Differential Output Main Link Output
TMDS_0 24(p), 23(n) O TMDS Data 0 Differential Output Main Link Output
TMDS_CLK 21(p), 20(n) O TMDS Data Clock Differential Output Main Link Output
SCL 17 I/O TMDS Port Bidirectional I
2
C Clock Line DDC Link (Sink)
SDA 16 I/O TMDS Port Bidirectional I
2
C Data Line DDC Link (Sink)
VCC 3, 9, 18, 22, 28 3.3 V Supply Voltage Supply
(1) (p) Positive; (n) Negative
(2) I
2
C bus data (n-SDA) and clock (p-SCL) lines.
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