Datasheet

www.ti.com
SDA
SCL
DataLine
Stable;
DataValid
ChangeofData Allowed
DataOutput
byTransmitter
DataOutput
byReceiver
SCL From
Master
START
Condition
ClockPulsefor
Acknowledgement
Not Acknowledge
Acknowledge
SCL
SDA
Acknowledge
Acknowledge
Slave Address
Data
SN75DP129
SLAS583A JANUARY 2008 REVISED MARCH 2008
Figure 24. I
2
C Bit Transfer
Figure 25. I
2
C Acknowledge
Figure 26. I
2
C Address and Data Cycles
During a read cycle, the slave receiver acknowledges the initial address byte if it decodes the address as its
address. Following this initial acknowledge by the slave, the master device becomes a receiver and
acknowledges data bytes sent by the slave. When the master has received all of the requested data bytes from
the slave, the not acknowledge (A) condition is initiated by the master by keeping the SDA signal high just before
it asserts the stop (P) condition. This sequence terminates a read cycle as shown in Figure 27 and Figure 28 .
See the Reading from the SN75DP129, an example section for more information.
Figure 27. I
2
C Read Cycle
18 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): SN75DP129