Datasheet

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TMDS and Main Link Pins
ELECTRICAL CHARACTERISTICS
SWITCHING CHARACTERISTICS
SN75DP129
SLAS583A JANUARY 2008 REVISED MARCH 2008
The main link inputs are designed to be compliant with the DisplayPort 1.1 specification. The TMDS outputs of
the SN75DP129 are designed to be compliant with the Digital Visual Interface 1.0 (DVI) and High Definition
Multimedia Interface 1.3 (HDMI) specifications. The differential output voltage swing can be fine-tuned with the
VSadj (TMDS-compliant Voltage Swing Control) resistor.
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
OH
Single-ended HIGH level output voltage AVCC 10 AVCC+10 mV
V
OL
Single-ended LOW level output voltage AVCC 600 AVCC 400 mV
V
SWING
Single-ended output voltage swing 400 600 mV
AVCC = 3.3 V, R
T
= 50
Change in steady-state common-mode
V
OC(SS)
5 5 mV
output voltage between logic states
V
OD(PP)
Peak-to-peak output differential voltage 800 1200 mV
AVCC = 3.3 V, R
T
= 50 ,
V
(O)SBY
Single-ended standby output voltage AVCC 10 AVCC+10 mV
LP = 0
0 V V
CC
1.5 V, AVCC = 3.3 V,
I
(O)OFF
Single-ended power down output current 10 10 µ A
R
T
= 50
I
OS
Short circuit output current V
ID
= 500 mV 15 15 mA
R
INT
Input termination impedance 45 50 55
V
term
Input termination voltage 1 2 V
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
PLH
Propagation delay time 250 350 600 ps
t
PHL
Propagation delay time 250 350 600 ps
t
R
Rise time 60 90 140 ps
t
F
Fall time AVCC = 3.3 V, R
T
= 50 , f = 1 MHz 60 90 140 ps
t
SK(P)
Pulse skew 8 15 ps
t
SK(D)
Intra-pair skew 20 40 ps
t
SK(O)
Inter-pair skew 20 65 ps
t
JITD(PP)
Peak-to-peak output residual data jitter AVCC = 3.3 V, R
T
= 50 , dR = 2.5 Gbps 14 50 ps
t
JITC(PP)
Peak-to-peak output residual clock jitter AVCC = 3.3 V, R
T
= 50 , f = 250 MHz 8 30 ps
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Product Folder Link(s): SN75DP129