Datasheet
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ELECTRICAL CHARACTERISTICS
SWITCHING CHARACTERISTICS
PULSE
GENERATOR
D.U.T.
R
T
V
OUT
V
CC
3.3V
R =2k
L
W
C =100pF
L
V
IN
SN75DP129
SLAS583A – JANUARY 2008 – REVISED MARCH 2008
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I
L
Low input current V
CC
= 3.6 V, V
I
= 0 V – 10 10 µ A
I
lkg(AUX)
Input leakage current AUX_I
2
C pins V
CC
= 3.6 V, V
I
= 3.6 V – 10 10 µ A
C
IO(AUX)
Input/output capacitance AUX_I
2
C pins DC bias = 1.65 V, AC = 2.1 V
p-p
, f = 100 kHz 15 pF
V
IH(AUX)
High-level input voltage AUX_I
2
C pins 1.6 5.5 V
V
IL(AUX)
Low-level input voltage AUX_I
2
C pins – 0.2 0.4 V
V
OL(AUX)
Low-level output voltage AUX_I
2
C pins I
O
= 4 mA 0.5 0.6 V
I
lkg(I2C)
Input leakage current I
2
C SDA/SCL pins V
CC
= 3.6 V, V
I
= 4.95 V – 10 10 µ A
C
IO(I2C)
Input/output capacitance I
2
C SDA/SCL pins DC bias = 2.5 V, AC = 3.5 V
p-p
, f = 100 kHz 15 pF
V
IH(I2C)
High-level input voltage I
2
C SDA/SCL pins 2.1 5.5 V
V
IL(I2C)
Low-level input voltage I
2
C SDA/SCL pins – 0.2 1.5 V
V
OL(I2C)
Low-level output voltage I
2
C SDA/SCL pins I
O
= 4 mA 0.2 V
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
PLH1
Propagation delay time, low to high Source to Sink 204 459 ns
t
PHL1
Propagation delay time, high to low Source to Sink 35 200 ns
t
PLH2
Propagation delay time, low to high Sink to Source 80 251 ns
t
PHL2
Propagation delay time, high to low Sink to Source 35 200 ns
t
f1
Output signal fall time Sink Side 20 72 ns
t
f2
Output signal fall time Source Side 20 72 ns
f
SCL
SCL clock frequency for internal register Source Side 100 kHz
t
W(L)
Clock LOW period for I
2
C register Source Side 4.7 µ s
t
W(H)
Clock HIGH period for internal register Source Side 4.0 µ s
t
SU1
Internal register setup time, SDA to SCL Source Side 250 ns
t
h(1)
Internal register hold time, SCL to SDA Source Side 0 µ s
t
(buf)
Internal register bus free time between STOP and START Source Side 4.7 µ s
t
su(2)
Internal register setup time, SCL to START Source Side 4.7 µ s
t
h(2)
Internal register hold time, START to SCL Source Side 4.0 µ s
t
su(3)
Internal register hold time, SCL to STOP Source Side 4.0 µ s
Figure 8. Source Side Test Circuit (AUX_I
2
C)
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