Datasheet

EXAMPLE – READING FROM THE SN75DP122A
SN75DP122A Read Phase:
SWITCHING LOGIC
SN75DP122A
www.ti.com ............................................................................................................................................................................................ SLLS939 – NOVEMBER 2008
The read operation consists of several steps. The I
2
C master begins the communication with the transmission of
the start sequence followed by the slave address of the SN75DP122A. The SN75DP122A acknowledges its
presence to the master and begin to transmit the contents of the memory registers. After each byte is transferred
the SN75DP122A waits for either an acknowledge (ACK) or a not-acknowledge (NACK) from the master. If an
ACK is received, the next byte of data is transmitted. If a NACK is received the data transmission sequence is
expected to end and the master should send the stop command.
The SN75DP122A continues to send data as long as the master continues to acknowledge each byte
transmission. If an ACK is received after the transmission of byte 0x0F, the SN75DP122A transmits byte 0x10
and continue to transmit byte 0x10 for all further ACK ’ s until a NACK is received.
Step 1 0
I
2
C Start (Master) S
Step 2 7 6 5 4 3 2 1 0
I
2
C General Address (Master) 1 0 0 0 0 0 0 1
Step 3 9
I
2
C Acknowledge (Slave) A
Step 10 7 6 5 4 3 2 1 0
I
2
C Read Data (Slave) Data Data Data Data Data Data Data Data
Where Data is determined by the logic values contained in the Sink port register
Step 11 9
I
2
C Not-Acknowledge (Master) X
Where X is either an A (Acknowledge) or A (Not-Acknowledge)
An A causes the pointer to increment and step 10 is repeated
An A causes the slave to stop transmitting and proceed to step 12
Step 12 0
I
2
C Stop (Master) P
The switching logic of the SN75DP122A is tied to the state of the HPD input pins as well as the priority pin and
low power pin. When both HPD_A and HPD_B input pins are LOW, the SN75DP122A enters the low power
state. In this state the outputs are high impedance, and the device is shutdown to optimize power conservation.
When either HPD_A or HPD_B goes high, the device enters the normal operational state, and the port
associated with the HPD pin that went high is selected. If both HPD_A and HPD_B are HIGH, the port selection
is determined by the state of the priority pin.
Several key factors were taken into consideration with this digital logic implementation of channel selection as
well as HPD repeating. This logic has been divided into the following four scenarios.
1. Low power state to active state. There are two possible cases for this scenario depending on the state of the
low power pin:
– Case one: In this case both HPD inputs are initially LOW and the low power pin is also LOW. In this initial
state the device is in a low power mode. Once one of the HPD inputs goes to a HIGH state, the device
remains in the low power mode with both the main link and auxiliary I/O in a high impedance state.
However, the port associated with the HPD input that went HIGH is still selected and the HPD output to
the source is enabled and follows the logic state of the input HPD (see Figure 37 ). The state of the
Priority pin has no effect in this scenario as only one HPD input port is active.
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