Datasheet

SDA
SCL
DataLine
Stable;
DataValid
ChangeofData Allowed
DataOutput
byTransmitter
DataOutput
byReceiver
SCL From
Master
START
Condition
ClockPulsefor
Acknowledgement
Not Acknowledge
Acknowledge
SCL
SDA
MSB
Acknowledge
Acknowledge
Stop
Slave Address
Data
SN75DP122A
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communication link with a slave has been established.
• The master generates further SCL cycles to either transmit data to the slave (R/W bit 0) or receive data from
the slave (R/W bit 1). In either case, the receiver needs to acknowledge the data sent by the transmitter. So
an acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long
as necessary (see Figure 34 ).
• To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low
to high while the SCL line is high (see Figure 31 ). This releases the bus and stops the communication link
with the addressed slave. All I
2
C compatible devices must recognize the stop condition. Upon the receipt of a
stop condition, all devices know that the bus is released, and they wait for a start condition followed by a
matching address.
Figure 32. I
2
C Bit Transfer
Figure 33. I
2
C Acknowledge
Figure 34. I
2
C Address and Data Cycles
During a read cycle, the slave receiver acknowledges the initial address byte if it decodes the address as its
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