Datasheet

APPLICATION INFORMATION
SWITCHING LOGIC
I
2
C INTERFACE NOTES
SDA
SCL
SDA
SCL
Start
Condition
Stop
Condition
GENERAL I
2
C PROTOCOL
SN75DP122A
SLLS939 – NOVEMBER 2008 ............................................................................................................................................................................................ www.ti.com
The Switching logic of the SN75DP122A is tied to the state of the HPD pins as well as the LP and priority pins.
When both HPD_A and HPD_B input pins are LOW, the SN75DP122A enters the low power state. In this state
the outputs are high impedance. When either HPD_A or HPD_B goes high, the device enters the normal
operational state and the port associated with the HPD pin that went high is selected. If both HPD_A and HPD_B
are HIGH, the port selection is determined by the state of the priority pin.
In order to ease the transitioning from one output port to the other output port the SN75DP122A forces the HPD
output pin LOW for an extended duration. This forced Low is designed to mimic an unplug event for the
transmitting device. This should allow for a smooth transition from one port to another. This forced LOW timer
can be bypassed by pulsing the LP pin LOW for a short duration and then returning to HIGH. When the LP pin if
driven LOW the device enters a low power state and the internal logic block is reset.
The I
2
C interface can be used to access the internal memory of the SN75DP122A. I
2
C is a two-wire serial
interface developed by Philips Semiconductor (see I
2
C-Bus Specification, Version 2.1, January 2000). The bus
consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and
SCL lines are pulled high. All the I
2
C compatible devices connect to the I
2
C bus through open drain I/O pins,
SDA and SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The
master is responsible for generating the SCL signal and device addresses. The master also generates specific
conditions that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on
the bus under control of the master device. The SN75DP122A works as a slave and supports the standard mode
transfer (100 kbps) and fast mode transfer (400 kbps) as defined in the I
2
C-Bus Specification.
The basic I
2
C start and stop access cycles are shown in Figure 31 .
The basic access cycle consists of the following:
• A start condition
• A slave address cycle
• Any number of data cycles
• A stop condition
Figure 31. I
2
C Start and Stop Conditions
• The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 31 . All I
2
C-compatible devices should
recognize a start condition.
• The master then generates the SCL pulses and transmits the 7-bit address and the read/write direction bit
R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition
requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 32 ). All devices
recognize the address sent by the master and compare it to their internal fixed addresses. Only the slave
device with a matching address generates an acknowledge (see Figure 33 ) by pulling the SDA line low during
the entire high period of the ninth SCL cycle. On detecting this acknowledge, the master knows that a
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