Datasheet

DATA FLOW BLOCK DIAGRAM
ML_IN 2(p)
ML_IN 2(n)
ML_IN 3(n)
ML_IN 3(p)
ML_IN 0(p)
ML_IN 0(n)
ML_IN 1(p)
ML_IN 1(n)
AUX(p)_I
2
C (SCL)
AUX(n)_I
2
C (SDA)
AUX_SINK (p)
AUX_SINK (n)
I
2
C_SCL
I
2
C_SDA
DP_SINK 0(n)
DP_SINK 0(p)
DP_SINK 3(p)
DP_SINK 3(n)
TMDS_SINK_CLK (p)
V
Sadj
Receiver
50 W
V
BIAS
I
2
C_SCL
I
2
C_SDA
TMDS_SINK_CLK (n)
TMDS_SINK 2(p)
TMDS_SINK 2(n)
Priority
DP_HPD_SINK
TMDS_HPD_SINK
HPD
CAD
CAD_SINK
Receiver
V
BIAS
Receiver
V
BIAS
Receiver
V
BIAS
Driver
Driver
Driver
Driver
Driver
Driver
Driver
Driver
2-to-1
MUX
Switching
Logic
I
2
CLogic
DP
Vadj
__
LP
50 W
50 W
50 W
50 W
50 W
50 W
50 W
SN75DP122A
SLLS939 – NOVEMBER 2008 ............................................................................................................................................................................................ www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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Product Folder Link(s): SN75DP122A