Datasheet

I
2
C_SCL/
I
2
C_SDA
Output
AUX_I
2
C(p)/
AUX_I
2
C(n)
Input
t
PHL1
0.5V
3.3V
1.6V
5V
TMDS MAIN LINK PINS
ELECTRICAL CHARACTERISTICS
SWITCHING CHARACTERISTICS
SN75DP122A
www.ti.com ............................................................................................................................................................................................ SLLS939 – NOVEMBER 2008
Figure 18. Sink Side Output AC Measurements Continued
The TMDS port of the SN75DP122A is designed to be compliant with the Digital Video Interface (DVI) 1.0 and
High Definition Multimedia Interface (HDMI) 1.3 specifications. The differential output voltage swing can be fine
tuned with the VSadj resistor.
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
OH
Single-ended HIGH level output voltage AVCC – 10 AVCC+10 mV
V
OL
Single-ended LOW level output voltage AVCC – 600 AVCC – 400 mV
V
SWING
Single-ended output voltage swing 400 600 mV
AVCC = 3.3 V, R
T
= 50 Ω
Change in steady-state common-mode output
V
OC(SS)
– 5 5 mV
voltage between logic states
V
OD(PP)
Peak-to-Peak output differential voltage 800 1200 mV
AVCC = 3.3 V, R
T
= 50 Ω ,
V
(O)SBY
Single-ended standby output voltage AVCC – 10 AVCC+10 mV
DP Port Selected
0 V ≤ VCC ≤ 1.5 V,
I
(O)OFF
Single-ended power down output current – 10 10 µ A
AVCC = 3.3 V, R
T
= 50 Ω
I
OS
Short circuit output current VID = 500 mV – 15 15 mA
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
PLH
Propagation delay time 250 480 600 ps
t
PHL
Propagation delay time 250 400 800 ps
t
R
Rise time 60 90 140 ps
t
F
Fall time AVCC = 3.3 V, R
T
= 50 Ω , f = 1 MHz 60 90 140 ps
t
SK(P)
Pulse skew 8 15 ps
t
SK(D)
Intra-pair skew 20 40 ps
t
SK(O)
Inter-pair skew 20 65 ps
t
JITD(PP)
Peak-to-peak output residual data jitter AVCC = 3.3 V, R
T
= 50 Ω , dR = 2.5 Gbps 20 50 ps
t
JITC(PP)
Peak-to-peak output residual clock jitter AVCC = 3.3 V, R
T
= 50 Ω , f = 250 MHz 10 30 ps
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