Datasheet
SWITCHING CHARACTERISTICS
PULSE
GENERATOR
R
T
V
IN
V
OUT
V
CC
D.U.T.
3.3V
R =2k
L
W
C
L
=100pF
SN75DP122A
www.ti.com
............................................................................................................................................................................................ SLLS939 – NOVEMBER 2008
ELECTRICAL CHARACTERISTICS (continued)
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input/output capacitance DC bias = 1 V, AC = 1.4 V
p-p
,
C
IO(AUX)
AUX_I
2
C pins 15 pF
f = 100 kHz
V
IH(AUX)
High-level input voltage AUX_I
2
C pins 1.6 V
V
IL(AUX)
Low-level input voltage AUX_I
2
C pins – 0.2 0.4 V
V
OL(AUX)
Low-level output voltage AUX_I
2
C pins I
O
= 4 mA 0.5 0.6 V
I
lkg(I2C)
Input leakage current I
2
C SDA/SCL pins V
CC
= 3.6 V, V
I
= 4.95V – 10 10 µ A
DC bias = 2.5 V,
C
IO(I2C)
Input/output capacitance I
2
C SDA/SCL pins 15 pF
AC = 3.5 V
p-p
, f = 100 kHz
V
IH(I2C)
High-level input voltage I
2
C SDA/SCL pins 2.1 V
V
IL(I2C)
Low-level input voltage I
2
C SDA/SCL pins -0.2 1.5 V
V
OL(I2C)
Low-level output voltage I
2
C SDA/SCL pins IO = 4 mA 0.2 V
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
PLH1
Propagation delay time, low to high Source to sink 204 459 ns
t
PHL1
Propagation delay time, high to low Source to sink 35 140 ns
t
PLH2
Propagation delay time, low to high Sink to source 80 251 ns
t
PHL2
Propagation delay time, high to low Sink to source 35 200 ns
t
f1
Output signal fall time Sink side 20 72 ns
t
f2
Output signal fall time Source side 20 72 ns
f
SCL
SCL clock frequency for internal register Source side 100 kHz
t
W(L)
Clock LOW period for I
2
C register Source side 4.7 µ s
t
W(H)
Clock HIGH period for internal register Source side 4.0 µ s
t
SU1
Internal register setup time, SDA to SCL Source side 250 ns
t
h(1)
Internal register hold time, SCL to SDA Source side 0 µ s
T
(buf)
Internal register bus free time between STOP and START Source side 4.7 µ s
t
su(2)
Internal register setup time, SCL to START Source side 4.7 µ s
t
h(2)
Internal register hold time, START to SCL Source side 4.0 µ s
t
su(3)
Internal register hold time, SCL to STOP Source side 4.0 µ s
Figure 14. Source Side Test Circuit (AUX_I
2
C)
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