Datasheet

MainLink
Input
MainLink
Output
ML_INx+
ML_INx-
0V
0V
t
PD(ML)
t
PD(ML)
ML x+
ML x-
ML y+
ML y-
2.2V
1.8V
2.2V
1.8V
50%
50%
T
sk1
T
sk2
T
sk1
TMDS I
2
C Pins
ELECTRICAL CHARACTERISTICS
SN75DP122A
SLLS939 – NOVEMBER 2008 ............................................................................................................................................................................................ www.ti.com
Figure 12. Main Link Delay Measurements
Figure 13. Main Link Skew Measurements
When the TMDS port is selected the SN75DP122A utilizes an I
2
C repeater. The repeater is designed to isolate
the parasitic effects of the system in order to aid with system level compliance.
In addition to the I
2
C repeater, the SN75DP122A also supports the connector detection I
2
C register. This register
is enabled via the I
2
C_EN pin. When active an internal memory register is readable via the AUX_I
2
C I/O. The
functionality of this register block is described in the application section
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I
L
Low input current V
CC
= 3.6 V, V
I
= 0 V – 10 10 µ A
I
lkg(AUX)
Input leakage AUX_I
2
C pins V
CC
= 3.6 V, V
I
= 3.6 V – 10 10 µ A
14 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): SN75DP122A