Datasheet
SLLS018E − JUNE 1986 − REVISED JUNE 2004
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
TEST CIRCUIT VOLTAGE WAVEFORMS
0.5 V
1 V
90%
0
0.8 V
3.5 V
V
OL
V
OH
3 V
2 V
1.5 V1.5 V
B Output
S1 to GND
S2 Closed
B Output
S1 to 3 V
S2 Open
TE Input
S2
5 V
Output
S1
3 V
PE
B
D
50 Ω
TE
Generator
(see Note A)
t
PLZ
t
PHZ
t
PZL
t
PZH
C
L
= 15 pF
(see Note B)
200 Ω
480 Ω
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, t
r
≤ 6 ns, t
f
≤ 6 ns
,
Z
O
= 50 Ω.
B. C
L
includes probe and jig capacitance.
Figure 3. TE-to-Bus Test Circuit and Voltage Waveforms
TEST CIRCUIT VOLTAGE WAVEFORMS
t
PLZ
t
PHZ
D Output
S1 to GND
S2 Closed
D Output
S1 to 3 V
S2 Open
TE Input
1 V
0.7 V
90%
V
OL
V
OH
4 V
0
0
3 V
1.5 V
S2
50 Ω
S1
3 V
Output
TE
B
D
Generator
(see Note A)
t
PZL
t
PZH
C
L
= 15 pF
(see Note B)
4.3 V
240 Ω
3 kΩ
1.5 V
1.5 V
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, t
r
≤ 6 ns, t
f
≤ 6 ns
,
Z
O
= 50 Ω.
B. C
L
includes probe and jig capacitance.
Figure 4. TE-to-Terminal Test Circuit and Voltage Waveforms