Datasheet


    
SLLS018E − JUNE 1986 − REVISED JUNE 2004
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Function Tables
EACH DRIVER
INPUTS
OUTPUT
D TE PE
OUTPUT
B
H H H H
L HX L
H XL Z
†
X L X Z
†
EACH RECEIVER
INPUTS
OUTPUT
B TE PE
OUTPUT
D
L L X L
H LX H
X H X Z
H = high level, L = low level, X = irrelevant,
Z = high-impedance state
†
This is the high-impedance state of a
normal 3-state output modified by the
internal resistors to V
CC
and GND.
logic diagram (positive logic)
PE
11
1
TE
GPIB
I/O
Ports
Terminal
I/O
Ports
B1
2
19
D1
B2
3
18
D2
B3
4
17
D3
B4
5
16
D4
B5
6
15
D5
B6
7
14
D6
D7
13
8
B7
9
12
D8
B8