Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - gate drivers NAND Low side SOIC 16 N



  

SLRS028A − SEPTEMBER 1988 − REVISED NOVEMBER 2004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Quadruple Circuits Capable of Driving

High-Capacitance Loads at High Speeds

D Output Supply Voltage Range From 5 V

to 24 V

D Low Standby Power Dissipation

D V

CC3

Supply Maximizes Output Source

Voltage

description/ordering information

The SN75374 is a quadruple NAND interface

circuit designed to drive power MOSFETs from

TTL inputs. It provides the high current and

voltage necessary to drive large capacitive loads

at high speeds.

The outputs can be switched very close to the V

CC2

supply rail when V

CC3

is about 3 V higher than V

CC2

. V

CC3

also can be tied directly to V

CC2

when the source voltage requirements are lower.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP (N) Tube of 25 SN75374N SN75374N

0°C to 70°C

SOIC (D)

Tube of 40 SN75374D

SN75374

0 C to 70 C

SOIC (D)

Reel of 2500 SN75374DR

SN75374

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

logic diagram (positive logic)

2E2

2E1

1E2

1E1

    !"   #!$% &"'

&!   #" #" (" "  ") !"

&& *+' &! #", &"  ""%+ %!&"

",  %% #""'

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

CC2

1E1

1E2

GND

CC1

2E2

2E1

CC3

D OR N PACKAGE

(TOP VIEW)

Summary of content (18 pages)

PAGE 1
SLRS028A − SEPTEMBER 1988 − REVISED NOVEMBER 2004 D Quadruple Circuits Capable of Driving D D D D OR N PACKAGE (TOP VIEW) High-Capacitance Loads at High Speeds Output Supply Voltage Range From 5 V to 24 V Low Standby Power Dissipation VCC3 Supply Maximizes Output Source Voltage VCC2 1Y 1A 1E1 1E2 2A 2Y GND description/ordering information The SN75374 is a quadruple NAND interface circuit designed to drive power MOSFETs from TTL inputs.
PAGE 2
SLRS028A − SEPTEMBER 1988 − REVISED NOVEMBER 2004 schematic (each driver) VCC1 VCC3 VCC2 To Other Drivers Input A Enable E1 Output Y Enable E2 GND To Other Drivers absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range (see Note 1): VCC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V VCC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 3
SLRS028A − SEPTEMBER 1988 − REVISED NOVEMBER 2004 electrical characteristics over recommended ranges of VCC1, VCC2, VCC3, and operating free-air temperature (unless otherwise noted) PARAMETER VIK VOH TEST CONDITIONS Input clamp voltage II = − 12 mA VCC3 = VCC2 + 3 V, High-level output voltage VCC3 = VCC2 + 3 V, VCC3 = VCC2, VCC3 = VCC2, VIH = 2 V, VIL = 0.8 V, VIL = 0.8 V, IOH = − 100 µA IOH = − 10 mA VIL = 0.8 V, VIL = 0.
PAGE 4
SLRS028A − SEPTEMBER 1988 − REVISED NOVEMBER 2004 PARAMETER MEASUREMENT INFORMATION 5V Input 24 V 20 V VCC1 VCC2 VCC3 RD Pulse Generator (see Note A) Output CL = 200 pF (see Note B) GND 2.4 V TEST CIRCUIT ≤10 ns ≤10 ns 3V 90% 90% Input 1.5 V 1.5 V 0.5 µs t PHL 10% t DHL 10% 0V t PLH t TLH t THL VCC2 − 2 V VOH VCC2 − 2 V t DLH Output 2V 2V VOLTAGE WAVEFORMS NOTES: A. The pulse generator has the following characteristics: PRR = 1 MHz, ZO ≈ 50 Ω . B.
PAGE 5
SLRS028A − SEPTEMBER 1988 − REVISED NOVEMBER 2004 TYPICAL CHARACTERISTICS HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT VCC2 VOH VOH − High-Level Output Voltage − V VOH VOH − High-Level Output Voltage − V VCC2 − 0.5 TA = 70°C −1 TA = 0°C − 1.5 ÁÁ ÁÁ −2 −3 − 0.01 −0.5 −1 TA = 25°C −1.5 ÁÁ ÁÁ VCC1 = 5 V VCC2 = 20 V VCC3 = 24 V VI = 0.8 V − 2.5 − 0.1 −1 − 10 VCC1 = 5 V VCC2 = VCC3 = 20 V V1 = 0.
PAGE 6
SLRS028A − SEPTEMBER 1988 − REVISED NOVEMBER 2004 TYPICAL CHARACTERISTICS PROPAGATION DELAY TIME LOW- TO HIGH-LEVEL OUTPUT vs FREE-AIR TEMPERATURE PROPAGATION DELAY TIME HIGH- TO LOW-LEVEL OUTPUT vs FREE-AIR TEMPERATURE 250 250 VCC1 = 5 V VCC2 = 20 V VCC3 = 24 V RD = 24 Ω See Figure 1 200 175 CL = 4000 pF 225 ttPLH PHL − Propagation Delay Time, High− to Low−Level Output − ns ttPLH PLH − Propagation Delay Time, Low- to High−Level Output − ns 225 CL = 2000 pF 150 125 100
PAGE 7
SLRS028A − SEPTEMBER 1988 − REVISED NOVEMBER 2004 TYPICAL CHARACTERISTICS PROPAGATION DELAY TIME LOW- TO HIGH-LEVEL OUTPUT vs LOAD CAPACITANCE PROPAGATION DELAY TIME HIGH- TO LOW-LEVEL OUTPUT vs LOAD CAPACITANCE 250 250 VCC1 = 5 V VCC2 = 20 V VCC3 = 24 V TA = 25°C See Figure 1 200 175 RD = 24 Ω 150 RD = 10 Ω 125 VCC1 = 5 V VCC2 = 20 V VCC3 = 24 V TA = 25°C See Figure 1 225 ttPLH PHL − Propagation Delay Time, High− to Low−Level Output − ns ttPLH PLH − Propagation Delay
PAGE 8
SLRS028A − SEPTEMBER 1988 − REVISED NOVEMBER 2004 THERMAL INFORMATION power-dissipation precautions Significant power may be dissipated in the SN75374 driver when charging and discharging high-capacitance loads over a wide voltage range at high frequencies. Figure 12 shows the power dissipated in a typical SN75374 as a function of frequency and load capacitance.
PAGE 9
SLRS028A − SEPTEMBER 1988 − REVISED NOVEMBER 2004 THERMAL INFORMATION power-dissipation precautions (continued) PL, PH, PLH, and PHL are the respective instantaneous levels of power dissipation, and C is the load capacitance. VC is the voltage across the load capacitance during the charge cycle shown by the equation: VC = VOH − VOL PS(AV) may be ignored for power calculations at low frequencies.
PAGE 10
SLRS028A − SEPTEMBER 1988 − REVISED NOVEMBER 2004 APPLICATION INFORMATION driving power MOSFETs The drive requirements of power MOSFETs are much lower than comparable bipolar power transistors. The input impedance of an FET consists of a reverse-biased PN junction that can be described as a large capacitance in parallel with a very high resistance. For this reason, the commonly used open-collector driver with a pullup resistor is not satisfactory for high-speed applications.
PAGE 11
SLRS028A − SEPTEMBER 1988 − REVISED NOVEMBER 2004 APPLICATION INFORMATION driving power MOSFETs (continued) Power MOSFET drivers must be capable of supplying high peak currents to achieve fast switching speeds as shown by the equation: I PK + VC tr where C is the capacitive load and tr is the desired rise time. V is the voltage that the capacitance is charged to.
PAGE 12
PACKAGE OPTION ADDENDUM www.ti.
PAGE 13
PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN75374DR Package Package Pins Type Drawing SOIC D 16 SPQ Reel Reel Diameter Width (mm) W1 (mm) 2500 330.0 16.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) 6.5 10.3 2.1 8.0 W Pin1 (mm) Quadrant 16.
PAGE 14
PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN75374DR SOIC D 16 2500 333.2 345.9 28.
PAGE 15
PAGE 16
PAGE 17
PAGE 18
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.