Datasheet
DS8830, SN55183, SN75183
DUAL DIFFERENTIAL LINE DRIVERS
SLLS093D – OCTOBER 1972 – REVISED APRIL 1998
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of V
CC
and operating free-air temperature
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
†
MAX UNIT
V
OH
High level out
p
ut voltage
Y (AND) out
p
uts
V
IH
=2V
I
OH
= –0.8 mA 2.4
V
V
OH
High
-
le
v
el
o
u
tp
u
t
v
oltage
Y
(AND)
o
u
tp
u
ts
V
IH
=
2
V
I
OH
= –40 mA 1.8 3.3
V
V
OL
Low level out
p
ut voltage
Y (AND) out
p
uts
V
IL
=08V
I
OL
= 32 mA 0.2
V
V
OL
Lo
w-
le
v
el
o
u
tp
u
t
v
oltage
Y
(AND)
o
u
tp
u
ts
V
IL
=
0
.
8
V
I
OL
= 40 mA 0.22 0.4
V
V
OH
High level out
p
ut voltage
Z (NAND) out
p
uts
V
IL
=08V
I
OH
= –0.8 mA 2.4
V
V
OH
High
-
le
v
el
o
u
tp
u
t
v
oltage
Z
(NAND)
o
u
tp
u
ts
V
IL
=
0
.
8
V
I
OH
= –40 mA 1.8 3.3
V
V
OL
Low level out
p
ut voltage
Z (NAND) out
p
uts
V
IH
=2V
I
OL
= 32 mA 0.2
V
V
OL
Lo
w-
le
v
el
o
u
tp
u
t
v
oltage
Z
(NAND)
o
u
tp
u
ts
V
IH
=
2
V
I
OL
= 40 mA 0.22 0.4
V
I
IH
High-level input current V
IH
= 2.4 V 120 µA
I
I
Input current at maximum input voltage V
IH
= 5.5 V 2 mA
I
IL
Low-level input current V
IL
= 0.4 V –4.8 mA
I
OS
Short-circuit output current
‡
V
CC
= 5 V, T
A
=125°C
§
–40 –100 –120 mA
I
CC
Supply current (average per driver) V
CC
= 5 V, All inputs at 5 V, No load 10 18 mA
†
All typical values are at V
CC
= 5 V, T
A
= 25°C.
‡
Not more than one output should be shorted to ground at a time, and duration of the short circuit should not exceed one second.
§
T
A
= 125°C is applicable to SN55183 only.
switching characteristics, V
CC
= 5 V, T
A
= 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
PLH
Propagation delay time, low- to high-level Y output AND gates
C
L
= 15 pF,
See FIgure 1(a)
8 12 ns
t
PHL
Propagation delay time, high- to low-level Y output AND gates
C
L
= 15 pF,
See FIgure 1(a)
12 18 ns
t
PLH
Propagation delay time, low- to high-level Z output NAND gates
C
L
= 15 pF,
See FIgure 1(a)
6 12 ns
t
PHL
Propagation delay time, high- to low-level Z output NAND gates
C
L
= 15 pF,
See FIgure 1(a)
6 8 ns
t
PLH
Propagation delay time,
low- to high-level differential output
Y output with respect to Z output,
R
L
= 100 Ω in series with 5000 pF,
See Figure 1(b)
9 16 ns
t
PHL
Propagation delay time,
high- to low-level differential output
Y output with respect to Z output,
R
L
= 100 Ω in series with 5000 pF,
See Figure 1(b)
8 16 ns