Datasheet

SN55182, SN75182
DUAL DIFFERENTIAL LINE RECEIVERS
SLLS092D – OCTOBER 1972 – REVISED APRIL 1998
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the J, N, and W packages.
&
3
1IN+
1
1IN–
RT
2
4
1STRB
RESP
5
1RTC
1OUT
6
11
2IN+
13
2IN–
12
10
2STRB
9
2RTC
2OUT
8
1R
T
2R
T
logic diagram (positive logic)
1OUT
3
1
2
5
4
1IN+
1IN–
1R
T
1RTC
1STRB
6
2OUT
11
13
12
9
10
2IN+
2IN–
2R
T
2RTC
2STRB
8
Pin numbers shown are for the J, N, and W packages.