Datasheet
SN75176A
DIFFERENTIAL BUS TRANSCEIVER
SLLS100A – JUNE 1984 – REVISED MAY 1995
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
RECEIVER SECTION
electrical characteristics over recommended ranges of common-mode input voltage, supply
voltage, and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
†
MAX UNIT
V
IT+
Positive-going input threshold voltage V
O
= 2.7 V, I
O
= –0.4 mA 0.2 V
V
IT–
Negative-going input threshold voltage V
O
= 0.5 V, I
O
= 8 mA –0.2
‡
V
V
hys
Input hysteresis voltage (V
IT+
– V
IT–
) 50 mV
V
IK
Enable clamp voltage I
I
= –18 mA –1.5 V
V
OH
High level out
p
ut voltage
V
ID
= 200 mV, I
OH
= –400
µ
A,
27
V
V
OH
High
-
le
v
el
o
u
tp
u
t
v
oltage
ID
,
See Figure 2
OH
µ ,
2
.
7
V
V
OL
Low level out
p
ut voltage
V
ID
= –200 mV, I
OL
= 8 mA,
045
V
V
OL
Lo
w-
le
v
el
o
u
tp
u
t
v
oltage
ID
,
See Figure 2
OL
,
0
.
45
V
I
OZ
High-impedance-state output current V
O
= 0.4 V to 2.4 V ±20 µA
I
I
Line in
p
ut current
Other input = 0 V,
V
I
= 12 V 1
mA
I
I
Line
inp
u
t
c
u
rrent
,
See Note 3
V
I
= –7 V –0.8
mA
I
IH
High-level enable input current V
IH
= 2.7 V 20 µA
I
IL
Low-level enable input current V
IL
= 0.4 V –100 µA
r
i
Input resistance 12 kΩ
I
OS
Short-circuit output current –15 –85 mA
I
CC
Su
pp
ly current (total
p
ackage)
No load
Outputs enabled 35 50
mA
I
CC
S
u
ppl
y
c
u
rrent
(total
package)
No
load
Outputs disabled 26 40
mA
†
All typical values are at V
CC
= 5 V, T
A
= 25°C.
‡
The algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used in this data sheet for common-mode
input voltage and threshold voltage levels only.
NOTE 3: This applies for both power on and power off. Refer to ANSI Standard EIA/TIA-422-B for exact conditions.
switching characteristics, V
CC
= 5 V, C
L
= 15 pF, T
A
= 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
PLH
Propagation delay time, low-to-high-level output
V
ID
= 15Vto15V
See Figure 6
21 35 ns
t
PHL
Propagation delay time, high-to-low-level output
V
ID
= –
1
.
5
V
to
1
.
5
V
,
See
Fig
u
re
6
23 35 ns
t
PZH
Output enable time to high level
See Figure 7
10 30 ns
t
PZL
Output enable time to low level
See
Fig
u
re
7
12 30 ns
t
PHZ
Output disable time from high level
See Figure 7
20 35 ns
t
PLZ
Output disable time from low level
See
Fig
u
re
7
17 25 ns