Datasheet

SN55173, SN65173, SN75173
QUADRUPLE DIFFERENTIAL LINE RECEIVERS
SLLS144E – OCTOBER 1980 – REVISED APRIL 2000
5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of common-mode input voltage, supply
voltage, and operating free-air temperature
PARAMETER TEST CONDITIONS MIN TYP
MAX UNIT
V
IT+
Positive-going input threshold voltage V
O
= 2.7 V, I
O
= –0.4 mA 0.2 V
V
IT–
Negative-going input threshold voltage V
O
= 0.5 V, I
O
= 16 mA 0.2
V
V
hys
Hysteresis (V
IT+
– V
IT–
) See Figure 4 50 mV
V
IK
Enable-input clamp voltage I
I
= –18 mA 1.5 V
SN55173 2.5 V
V
OH
High-level output voltage V
ID
= 200 mV, I
OH
= –400 µA
SN65173,
SN75173
2.7 V
V
OL
Low level out
p
ut voltage
V
ID
= 200 mV
See Figure 1
I
OL
= 8 mA 0.45
V
OL
Lo
w-
le
v
el
o
u
tp
u
t
v
oltage
V
ID
= –
200
mV
,
See
Fig
u
re
1
I
OL
= 16 mA 0.5
I
OZ
High-impedance-state output current V
O
= 0.4 V to 2.4 V ±20 µA
I
I
Line in
p
ut current
Other in
p
ut at 0 V
See Note 3
V
I
= 12 V 1
I
I
Line
inp
u
t
c
u
rrent
Other
inp
u
t
at
0
V
,
See
Note
3
V
I
= –7 V 0.8
I
IH
High-level enable-input current V
IH
= 2.7 V 20 µA
I
IL
Low-level enable-input current V
IL
= 0.4 V 100 µA
r
i
Input resistance 12 k
I
OS
Short-circuit output current –15 –85 mA
I
CC
Supply current Outputs disabled 70 mA
All typical values are at V
CC
= 5 V, T
A
= 25°C.
The algebraic convention, in which the less positive (more negative) limit is designated as minimum, is used in this data sheet for threshold voltage
levels only.
NOTE 3: Refer to TIA/EIA-422-B and TIA/EIA-423-B for exact conditions.
switching characteristics, V
CC
= 5 V, T
A
= 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
PLH
Propagation delay time, low-to-high-level output
V
ID
= –1.5 V to 1.5 V,
20 35 ns
t
PHL
Propagation delay time, high-to-low-level output
ID
,
C
L
= 15 pF, See Figure 1
22 35 ns
t
PZH
Output enable time to high level C
L
= 15 pF, See Figure 2 17 22 ns
t
PZL
Output enable time to low level C
L
= 15 pF, See Figure 3 20 25 ns
t
PHZ
Output disable time from high level C
L
= 5 pF, See Figure 2 21 30 ns
t
PLZ
Output disable time from low level C
L
= 5 pF, See Figure 3 30 40 ns