Datasheet

SN75154
QUADRUPLE LINE RECEIVER
SLLS083B – NOVEMBER 1970 – REVISED MAY 1995
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
THRS ADJ
4T
4A
3T
3A
2T
2A
1T
1A
10
11
12
13
4Y
3Y
2Y
1Y
14
7
1
6
2
5
3
4
†
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
logic diagram (positive logic)
14
7
1
6
2
5
3
4
4T
4A
3T
3A
2T
2A
1T
1A
10
11
12
13
4Y
3Y
2Y
1Y
schematic
Component values shown are nominal.
V
CC2
‡
V
CC1
R1
GND
Threshold
Input
Control
Common to Four Receivers
1 of 4 Receivers
5 kΩ
3.2 kΩ
5.5 kΩ
5 kΩ
1.6 kΩ 1.6 kΩ 200 Ω
4.2 kΩ
2.7 kΩ
1 kΩ
240 Ω
Output
9.9 kΩ
. . . Substrate
‡
When V
CC1
is used, V
CC2
may be left open or shorted to V
CC1
. When V
CC2
is used, V
CC1
must be left open
or connected to the threshold control pins.