Datasheet

SN74VMEH22501A

SCES3620A –DECEMBER 2004–REVISED FEBRUARY 2010

www.ti.com

VMEbus Summary

In 1981, the VMEbus was introduced as a backplane bus architecture for industrial and commercial applications.

The data-transfer protocols used to define the VMEbus came from the Motorola™ VERSA bus architecture that

owed its heritage to the then recently introduced Motorola 68000 microprocessor. The VMEbus, when

introduced, defined two basic data-transfer operations: single-cycle transfers consisting of an address and a data

transfer, and a block transfer (BLT) consisting of an address and a sequence of data transfers. These transfers

were asynchronous, using a master-slave handshake. The master puts address and data on the bus and waits

for an acknowledgment. The selected slave either reads or writes data to or from the bus, then provides a

data-acknowledge (DTACK*) signal. The VMEbus system data throughput was 40 Mbyte/s. Previous to the

VMEbus, it was not uncommon for the backplane buses to require elaborate calculations to determine loading

and drive current for interface design. This approach made designs difficult and caused compatibility problems

among manufacturers. To make interface design easier and to ensure compatibility, the developers of the

VMEbus architecture defined specific delays based on a 21-slot terminated backplane and mandated the use of

certain high-current TTL drivers, receivers, and transceivers.

In 1989, multiplexing block transfer (MBLT) effectively increased the number of bits from 32 to 64, thereby

doubling the transfer rate. In 1995, the number of handshake edges was reduced from four to two in the

double-edge transfer (2eVME) protocol, doubling the data rate again. In 1997, the VMEbus International Trade

Association (VITA) established a task group to specify a synchronous protocol to increase data-transfer rates to

320 Mbyte/s, or more. The unreleased specification, VITA 1.5 [double-edge source synchronous transfer

(2eSST)], is based on the asynchronous 2eVME protocol. It does not wait for acknowledgement of the data by

the receiver and requires incident-wave switching. Sustained data rates of 1 Gbyte/s, more than ten times faster

than traditional VME64 backplanes, are possible by taking advantage of 2eSST and the 21-slot VME320

star-configuration backplane. The VME320 backplane approximates a lumped load, allowing substantially

higher-frequency operation over the VME64x distributed-load backplane. Traditional VME64 backplanes with no

changes theoretically can sustain 320 Mbyte/s.

From BLT to 2eSST – A Look at the Evolution of VMEbus Protocols by John Rynearson, Technical Director,

VITA, provides additional information on VMEbus and can be obtained at www.vita.com.

Maximum Data Transfer Rates

FREQUENCY (MHz)

DATA BITS DATA TRANSFERS PER SYSTEM

DATE TOPOLOGY PROTOCOL

PER CYCLE PER CLOCK CYCLE (Mbyte/s)

BACKPLANE CLOCK

1981 VMEbus IEEE-1014 BLT 32 1 40 10 10

1989 VME64 MBLT 64 1 80 10 10

1995 VME64x 2eVME 64 2 160 10 20

1997 VME64x 2eSST 64 2-No Ack 160–320 10–20 20–40

1999 VME320 2eSST 64 2-No Ack 320–1000 20–62.5 40–125

Applicability

Target applications for VME backplanes include industrial controls, telecommunications, simulation, high-energy

physics, office automation, and instrumentation systems.

Product Folder Link(s): SN74VMEH22501A