Datasheet

SN74V263, SN74V273, SN74V283, SN74V293
8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions (Continued)
TERMINAL
I/O
DESCRIPTION
NAME
I/O
DESCRIPTION
PFM I
Programmable-flag mode. During master reset, a low on PFM selects asynchronous programmable-flag timing
mode. A high on PFM selects synchronous programmable-flag timing mode.
PRS I
Partial reset. PRS initializes the read and write pointers to zero and sets the output register to all zeroes. During
partial reset, the existing mode (standard or FWFT), programming method (serial or parallel), and
programmable-flag settings, input and output bus widths, big/little endian, interspersed parity select, and retransmit
mode are all retained.
Q0–Q17 O
Data outputs. Data outputs for a 18- or 9-bit bus. When in 18-bit mode, Q0–Q17 are used and when in 9-bit mode,
Q0–Q8 are used, and the unused outputs, Q9–Q17 should not be connected. Outputs are not 5-V tolerant regardless
of the state of OE
.
RCLK I
Read clock. When enabled by REN, the rising edge of RCLK reads data from the FIFO memory and offsets from
the programmable registers.
REN I Read enable. REN enables RCLK for reading data from the FIFO memory and offset registers.
RM I
Retransmit latency mode. During master reset, a low on RM selects zero-latency retransmit timing mode. A high on
RM selects normal-latency mode.
RT I
Retransmit. RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF flag to low (OR
to high in FWFT mode) and does not disturb the write pointer, programming method, existing timing mode, or
programmable flag settings. RT
is useful to reread data starting from the first physical location of the FIFO.
SEN I Serial enable. SEN enables serial loading of programmable flag offsets.
WCLK I
Write clock. When enabled by WEN, the rising edge of WCLK writes data into the FIFO and offsets into the
programmable registers for parallel programming and, when enabled by SEN
, the rising edge of WCLK writes one
bit of data into the programmable register for serial programming.
WEN I Write enable. WEN enables WCLK for writing data into the FIFO memory and offset registers.
detailed description
inputs
data in (D0–Dn)
Data inputs for 18-bit-wide data (D0–D17) or data inputs for 9-bit wide data (D0–D8).
controls
master reset (MRS
)
A master reset is accomplished when the MRS
input is taken to a low state. This operation sets the internal read
and write pointers to the first location of the RAM array. PAE
goes low, PAF goes high, and HF goes high.
If FWFT/SI is high, the FWFT mode, along with IR
and OR, is selected. OR goes high and IR goes low. If
FWFT/SI is low during master reset, the standard mode, along with EF
and FF, is selected. EF goes low and
FF
goes high.
All control settings, such as OW, IW, BE
, RM, PFM, and IP, are defined during the master reset cycle.
During a master reset, the output register is initialized to all zeroes. A master reset is required after power up,
before a write operation can take place. MRS
is asynchronous.
See Figure 5 for timing information.