Datasheet

SN74V263, SN74V273, SN74V283, SN74V293
8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
Also, the timing modes of PAE and PAF outputs can be selected. Timing modes can be set to be either
asynchronous or synchronous for PAE
and PAF.
If the asynchronous PAE
/PAF configuration is selected, PAE is asserted low on the low-to-high transition of
RCLK. PAE
is reset to high on the low-to-high transition of WCLK. Similarly, PAF is asserted low on the
low-to-high transition of WCLK, and PAF
is reset to high on the low-to-high transition of RCLK.
If the synchronous PAE
/PAF configuration is selected , PAE is asserted and updated on the rising edge of RCLK
only and not WCLK. Similarly, PAF
is asserted and updated on the rising edge of WCLK only and not RCLK.
The desired mode is configured during master reset by the state of the programmable-flag mode (PFM) pin.
The retransmit function allows data to be reread from the FIFO more than once. A low on the RT
input during
a rising RCLK edge initiates a retransmit operation by setting the read pointer to the first location of the memory
array. Zero-latency retransmit timing mode can be selected using the retransmit timing mode (RM). During
master reset, a low on RM selects zero-latency retransmit. A high on RM during master reset selects normal
latency.
If zero-latency retransmit operation is selected, the first data word to be retransmitted is placed on the output
register with respect to the same RCLK edge that initiated the retransmit, if RT
is low.
During master reset (MRS
), the functions for all the operating modes are programmed. These include FWFT
or standard timing, input bus width, output bus width, big endian or little endian, retransmit mode,
programmable-flag operating and programming method, programmable-flag default offsets, and interspersed
parity select. The read and write pointers are set to the first location of the FIFO. Then, based on the selected
timing mode, EF
is set low or OR is set high and FF is set high or IR is set low. Also, PAE is set low, PAF is set
high, and HF
is set high. The Q outputs are set low.
Partial reset (PRS
) also sets the read and write pointers to the first location of the memory. However, the timing
mode, programmable-flag programming method, default or programmed offset settings, input and output bus
widths, big endian/little endian, interspersed parity select, and retransmit mode existing before partial reset is
asserted remain unchanged. The flags are updated according to the timing mode and offsets in effect. PRS
is
useful for resetting a device in mid-operation when reprogramming programmable flags and other functions
would be undesirable.