Datasheet

SN74V263, SN74V273, SN74V283, SN74V293
8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003
45
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
optional configurations
width expansion configuration
Word width can be increased by connecting the control signals of multiple devices. Status flags can be detected
from any one device. The exceptions are the the IR
and OR functions in FWFT mode and EF and FF functions
in standard mode. Because of variations in skew between RCLK and WCLK, it is possible for EF
/FF deassertion
and IR
/OR assertion to vary by one cycle between FIFOs. In standard mode, such problems can be avoided
by creating composite flags, that is, ANDing EF
of every FIFO and separately ANDing FF of every FIFO. In
FWFT mode, composite flags can be created by ORing OR
of every FIFO and separately ORing IR of every
FIFO.
Figure 23 demonstrates a width expansion using two SN74V263, SN74V273, SN74V283, and SN74V293
devices. If ×18 input or ×18 output bus width is selected, D0–D17 from each device form a 36-bit-wide input bus,
and Q0–Q17 from each device form a 36-bit-wide output bus. If both ×9 input and ×9 output bus widths are
selected, D0–D8 from each device form an 18-bit-wide input bus, and Q0–Q8 from each device form an
18-bit-wide output bus. Any word width can be attained by adding additional SN74V263, SN74V273,
SN74V283, and SN74V293 devices.
Read Clock (RCLK)
Read Enable (REN
)
Output Enable (OE
)
Write Clock (WCLK)
Retransmit (RT
)
Half-Full Flag (HF
)
Write Enable (WEN)
Load (LD
)
First-Word Fall-Through or Serial Input
(FWFT/SI)
Programmable
Almost-Full Flag (PAF
)
Data In
Partial Reset (PRS)
Master Reset (MRS
)
m + n
Full Flag/Input Ready 2
(FF
/IR)
Full Flag/Input Ready 1
(FF
/IR)
Empty Flag/Output Ready 2
(EF/OR)
D0–Dm
m
(Dm + 1) – Dn
n
Q0–Qm
m
n
(Qm + 1) – Qn
m + n
Data Out
SN74V263
SN74V273
SN74V283
SN74V293
SN74V263
SN74V273
SN74V283
SN74V293
Programmable (PAE)
Empty Flag/Output Ready 1
(EF
/OR)
Gate
Gate
NOTES: A. Use an OR gate in FWFT mode and an AND gate in standard mode.
B. Do not connect any output control signals together directly.
C. FIFO 1 and FIFO 2 must be the same depth, but can be different word widths.
(see Note A)
(see Note A)
FIFO 1 FIFO 2
Figure 23. Width-Expansion Block Diagam
(For the ×18 Input or ×18 Output Bus Width: 8192 × 36, 16384 × 36, 32768 × 36, and 65536 × 36)
(For Both ×9 Input and ×9 Output Bus Widths: 16284 × 18, 32768 × 18, 65536 × 18, and 131072 × 18)