Datasheet

SN74V263, SN74V273, SN74V283, SN74V293
8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003
43
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
n + 1 Words in FIFO
(see Note B)
n + 2 Words in FIFO
(see Note C)
n Words in FIFO
(see Note B)
n + 1 Words in FIFO
(see Note C)
WCLK
WEN
PAE
RCLK
REN
t
CLKL
t
ENS
t
ENH
t
PAEA
n Words in FIFO (see Note B)
n+1 Words in FIFO (see Note C)
t
ENS
t
PAEA
NOTES: A. n = PAE offset
B. For standard mode
C. For FWFT mode
D. PAE
is asserted low on RCLK transition and reset to high on WCLK transition.
E. Select this mode by setting PFM low during master reset.
t
CLKH
Figure 21. Asynchronous Programmable Almost-Empty Flag Timing (FWFT and Standard Modes)