Datasheet

SN74V263, SN74V273, SN74V283, SN74V293
8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003
42
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
t
ENS
t
ENH
D – (m + 1) Words in FIFO
D – m Words in FIFO
WCLK
WEN
PAF
RCLK
REN
t
CLKH
t
ENS
t
PAFA
t
PAFA
D – (m + 1) Words in FIFO
t
CLKL
NOTES: A. m = PAF offset
B. D = maximum FIFO depth
In FWFT mode: If ×18 input or ×18 output bus width is selected, D = 8193 for the SN74V263, D = 16385 for the SN74V273,
D = 32769 for the SN74V283, and D = 65537 for the SN74V293. If both ×9 input and ×9 output bus widths are selected, D = 16385
for the SN74V263, D = 32769 for the SN74V273, D = 65537 for the SN74V283, and D = 131073 for the SN74V293.
In standard mode: If ×18 input or ×18 output bus width is selected, D = 8192 for the SN74V263, D = 16384 for the SN74V273,
D = 32768 for the SN74V283, and D = 65536 for the SN74V293. If both ×9 input and ×9 output bus widths are selected, D = 16384
for the SN74V263, D = 32768 for the SN74V273, D = 65536 for the SN74V283, and D = 131072 for the SN74V293.
C. PAF
is asserted to low on WCLK transition and reset to high on RCLK transition.
D. Select this mode by setting PFM low during master reset.
Figure 20. Asynchronous Programmable Almost-Full Flag Timing (FWFT and Standard Modes)