Datasheet

SN74V263, SN74V273, SN74V283, SN74V293
8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003
41
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
t
CLKL
t
ENH
n Words in FIFO (see Note B)
n + 1 Words in FIFO (see Note C)
t
sk2
(see Note D)
WCLK
WEN
RCLK
12 1 2
REN
t
ENS
t
PAES
n Words in FIFO (see Note B)
n + 1 Words in FIFO (see Note C)
t
PAES
t
ENS
t
ENH
n Words in FIFO (see Note B)
n + 1 Words in FIFO (see Note C)
NOTES: A. n = PAE offset
B. For standard mode
C. For FWFT mode
D. t
sk2
is the minimum time between a rising WCLK edge and a rising RCLK edge to ensure that PAE
goes high (after one RCLK
cycle + t
PAES
). If the time between the rising edge of WCLK and the rising edge of RCLK is less than t
sk2
, the PAE
deassertion
can be delayed one additional RCLK cycle.
E. PAE
is asserted and updated on the rising edge of RCLK only.
F. Select this mode by setting PFM high during master reset.
PAE
t
CLKH
Figure 19. Synchronous Programmable Almost-Empty Flag Timing (FWFT and Standard Modes)