Datasheet

SN74V263, SN74V273, SN74V283, SN74V293
8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003
40
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
t
sk2
(see Note C)
D – (m + 1) Words in FIFO
(see Notes A and B)
D – (m + 1)
Words in
FIFO
(see Notes
A and B)
WCLK
WEN
PAF
RCLK
REN
1
2
12
t
CLKL
t
ENS
t
ENH
t
PAFS
t
PAES
t
ENS
t
ENH
D – m Words in FIFO
(see Notes A and B)
t
CLKH
NOTES: A. m = PAF offset
B. D = maximum FIFO depth
In FWFT mode: If ×18 input or ×18 output bus width is selected, D = 8193 for the SN74V263, D = 16385 for the SN74V273,
D = 32769 for the SN74V283, and D = 65537 for the SN74V293. If both ×9 input and ×9 output bus widths are selected, D = 16385
for the SN74V263, D = 32769 for the SN74V273, D = 65537 for the SN74V283, and D = 131073 for the SN74V293.
In standard mode: If ×18 input or ×18 output bus width is selected, D = 8192 for the SN74V263, D = 16384 for the SN74V273,
D = 32768 for the SN74V283, and D = 65536 for the SN74V293. If both ×9 Input and ×9 output bus widths are selected, D = 16384
for the SN74V263, D = 32768 for the SN74V273, D = 65536 for the SN74V283, and D = 131072 for the SN74V293.
C. t
sk2
is the minimum time between a rising RCLK edge and a rising WCLK edge to ensure that PAF
goes high (after one WCLK
cycle + t
PAFS
). If the time between the rising edge of RCLK and the rising edge of WCLK is less than t
sk2
, the PAF
deassertion
time may be delayed one additional WCLK cycle.
D. PAF
is asserted and updated on the rising edge of WCLK only.
E. Select this mode by setting PFM high during master reset.
Figure 18. Synchronous Programmable Almost-Full Flag Timing (FWFT and Standard Modes)