Datasheet

SN74V263, SN74V273, SN74V283, SN74V293
8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
Write-Control
Logic
RAM Array
8192 × 18 or 16384 × 9
16384 × 18 or 32768 × 9
32768 × 18 or 65536 × 9
65536 × 18 or 131072 × 9
Offset
Register
Input
Register
Flag
Logic
Read Pointer
Read-Control Logic
Output
Register
Write
Pointer
Control
Logic
Reset
Logic
BE
IP
MRS
WEN
WCLK
D0–Dn (×9 or ×18)
SEN
HF
PAE
EF/OR
PAF
FF/IR
Q0–Qn (×9 or ×18)
OE
RENRCLK
Bus
Configuration
IW
OW
PRS
LD
FSEL1
FSEL0
PFM
FWFT/SI
RM
RT
description (continued)
For applications requiring more data-storage capacity than a single FIFO can provide, the FWFT timing mode
permits depth expansion by chaining FIFOs in series (i.e., the data outputs of one FIFO are connected to the
corresponding data inputs of the next). No external logic is required.
These FIFOs have five flag pins: empty flag or output ready (EF
/OR), full flag or input ready (FF/IR), half-full
flag (HF
), programmable almost-empty flag (PAE), and programmable almost-full flag (PAF). The IR and OR
functions are selected in FWFT mode. The EF and FF functions are selected in standard mode. HF, PAE, and
PAF
always are available for use, regardless of timing mode.
PAE
and PAF can be programmed independently to switch at any point in memory. Programmable offsets
determine the flag-switching threshold and can be loaded by parallel or serial methods. Eight default offset
settings also are provided, so that PAE
can be set to switch at a predefined number of locations from the empty
boundary. The PAF
threshold also can be set at similar predefined values from the full boundary. The default
offset values are set during master reset by the state of FSEL0, FSEL1, and LD
.
For serial programming, SEN
, together with LD, loads the offset registers via the serial input (SI) on each rising
edge of WCLK. For parallel programming, WEN
, together with LD, loads the offset registers via Dn on each
rising edge of WCLK. REN
, together with LD, can read the offsets in parallel from Qn on each rising edge of
RCLK, regardless of whether serial or parallel offset loading has been selected.