Datasheet

SN74V263, SN74V273, SN74V283, SN74V293
8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003
39
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PAF Offset (MSB)
t
LDS
RCLK
LD
REN
Data In Output Register PAE Offset (LSB) PAE Offset (MSB) PAF Offset (LSB)
t
ENH
t
LDH
t
LDH
t
ENH
Q0–Q16
t
CLKL
t
CLK
t
A
t
A
t
A
t
A
NOTES: A. OE = low
B. This diagram is based on programming the SN74V293 ×18 bus width. Add one additional cycle to both the PAE
offset and PAF
offset for ×9 bus width.
t
CLKH
t
ENS
Figure 17. Parallel Read of Programmable Flag Registers (FWFT and Standard Modes)