Datasheet

SN74V263, SN74V273, SN74V283, SN74V293
8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003
38
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Bit x
(see Note A)
Bit 0Bit x
(see Note A)
WCLK
SEN
SI
LD
t
ENS
t
ENH
t
ENH
t
LDH
t
LDS
t
LDH
t
DH
t
DS
Empty Offset Full Offset
Bit 0
NOTES: A. ×9 to ×9 mode: x = 13 for the SN74V263, x = 14 for the SN74V273, x = 15 for the SN74V283, and x = 16 for the SN74V293
B. All other modes: x = 12 for the SN74V263, x = 13 for the SN74V273, x = 14 for the SN74V283, and x = 15 for the SN74V293
Figure 15. Serial Loading of Programmable Flag Registers (FWFT and Standard Modes)
WCLK
LD
WEN
PAE Offset (MSB) PAF Offset (LSB)PAE Offset (LSB) PAF Offset (MSB)
t
CLK
t
LDS
t
LDH
t
ENS
t
DS
t
DH
t
ENH
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
t
LD
H
t
ENH
D0–D16
NOTE A: This diagram is based on programming the SN74V293 ×18 bus width. Add one additional cycle to both the PAE offset and PAF offset
for ×9 bus width.
t
CLKH
t
CLKL
Figure 16. Parallel Loading of Programmable Flag Registers (FWFT and Standard Modes)