Datasheet

SN74V263, SN74V273, SN74V283, SN74V293
8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003
37
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
W1 W2 (see Note D) W3 (see Note D) W4 (see Note D)
WCLK
RCLK
REN
RT
OR
PAF
HF
PAE
12
1
2
WEN
4
5
3
t
ENS
t
ENH
t
sk2
t
ENS
t
ENH
t
HF
t
PAES
t
PAFS
Q0–Qn Wx Wx + 1 W5
t
A
t
A
t
A
t
A
t
A
t
RTS
NOTES: A. If the part is empty at the point of retransmit, OR
is updated based on RCLK (retransmit clock cycle). Valid data also appears on
the output.
B. No more than (D – 2) words may be written to the FIFO between reset (master or partial) and retransmit setup. Therefore, IR is
low throughout the retransmit setup procedure.
If ×18 input or ×18 output bus width is selected, D = 8193 for the SN74V263, D = 16385 for the SN74V273, D = 32769 for the
SN74V283, and D = 65537 for the SN74V293.
If both ×9 input and ×9 output bus widths are selected, D = 16385 for the SN74V263, D = 32769 for the SN74V273, D = 65537
for the SN74V283, and D = 131073 for the SN74V293.
C. OE
= low
D. W
1
, W
2
, W
3
= first, second, and third words written to the FIFO after master reset.
E. There must be at least two words written to the FIFO before a retransmit operation can be invoked.
F. RM is set low during MRS
.
Figure 14. Zero-Latency Retransmit Timing (FWFT Mode)