Datasheet

SN74V263, SN74V273, SN74V283, SN74V293
8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003
36
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
WCLK
RCLK
REN
RT
PAF
HF
PAE
12
1
2
WEN
3
t
ENS
t
ENH
t
A
t
A
t
A
t
A
t
A
t
sk2
t
RTS
t
ENS
t
ENH
t
HF
t
PAES
Q0–Qn Wx Wx + 1 W1 W4
EF
(
see Note A)
t
PAFS
W3 (see Note C)
NOTES: A. If the FIFO is empty at the point of retransmit, EF
is updated based on RCLK (retransmit clock cycle). Valid data also appears
on the output.
B. OE = low, enables data to be read on outputs Q0–Qn
C. W
2
= second word written to the FIFO after master reset, W3 = third word written to the FIFO after master reset
D. No more than (D – 2) words may be written to the FIFO between reset (master or partial) and retransmit setup. Therefore, FF
is
high throughout the retransmit setup procedure.
If ×18 input or ×18 output bus width is selected, D = 8192 for the SN74V263, D = 16384 for the SN74V273, D = 32768 for the
SN74V283, and D = 65536 for the SN74V293.
If both ×9 input and ×9 output bus widths are selected, D = 16384 for the SN74V263, D = 32768 for the SN74V273, D = 65536
for the SN74V283, and D = 131072 for the SN74V293.
E. There must be at least two words written to and read from the FIFO before a retransmit operation can be invoked.
F. RM is set low during MRS
.
W2 (see Note C)
Figure 13. Zero-Latency Retransmit Timing (Standard Mode)