Datasheet

SN74V263, SN74V273, SN74V283, SN74V293
8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003
35
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
WCLK
RCLK
REN
RT
OR
PAF
HF
PAE
12
1 2
WEN
3
4
t
ENS
t
ENH
t
RTS
t
ENS
t
ENH
t
A
t
A
t
sk2
t
ENS
t
ENH
t
REF
t
REF
t
PAES
t
HF
Q0–Qn
Wx Wx + 1 W4
t
PAFS
t
RTS
t
A
t
A
W1 (see Note D) W2 (see Note D) W3 (see Note D)
NOTES: G. Retransmit setup is complete after OR returns low.
H. No more than (D – 2) words can be written to the FIFO between reset (master or partial) and retransmit setup. Therefore, IR
is
low throughout the retransmit setup procedure.
If ×18 input or ×18 output bus width is selected, D = 8193 for the SN74V263, D = 16385 for the SN74V273, D = 32769 for the
SN74V283, and D = 65537 for the SN74V293
If both ×9 input and ×9 output bus widths are selected, D = 16385 for the SN74V263, D = 32769 for the SN74V273, D = 65537
for the SN74V283, and D = 131073 for the SN74V293.
I. OE
= low
J. W
1
, W
2
, W
3
= first, second, and third words written to the FIFO after master reset
K. There must be at least two words written to the FIFO before a retransmit operation can be invoked.
L. RM is set high during MRS
.
Figure 12. Retransmit Timing (FWFT Mode)