Datasheet

SN74V263, SN74V273, SN74V283, SN74V293
8192 18, 16384 18, 32768 18, 65536 18
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003
×
×
×
×
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
• 33
t
OE
WCLK
WD
t
ENH
t
ENS
WEN
t
sk1
(see Note A)
12
t
DH
t
DS
D0–D17
RCLK
t
ENS
t
ENS
REN
OE
t
OHZ
t
A
t
A
t
A
t
A
t
A
t
A
t
REF
Q0–Q17
t
PAES
t
HF
t
PAFS
t
WFF
t
WFF
OR
PAE
HF
PAF
IR
W1
W1 W2
W3
W[m+3]Wm+2 W[m+4]
D – 1
+ 1
W
2
D – 1
+ 2
W
2
W[D-n-1] W[D-n] W[D-n+2] W[D-1]
WD
NOTES: A. t
sk1
is the minimum time between a rising RCLK edge and a rising WCLK edge to ensure that IR goes low after one WCLK cycle + t
WFF
. If the time between the rising
edge of RLCK and the rising edge of WCLK is less than t
sk1
, IR
assertion might be delayed an additional WCLK cycle.
B. t
sk2
is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF
to go high after one WCLK cycle + t
PAFS
. If the time between the rising edge
of RCLK and the rising edge of WCLK is less than t
sk2
, PAF
deassertion may be delayed an additional WCLK cycle.
C. LD
= high
D. n = PAE
offset, m = PAF offset, D = maximum FIFO depth
E. If ×18 input or ×18 output bus width is selected, D = 8193 for the SN74V263, D = 16385 for the SN74V273, D = 32769 for the SN74V283, and D = 65537 for the
SN74V293. If both ×9 input and ×9 output bus widths are selected, D = 16385 for the SN74V263, D = 32769 for the SN74V273, D = 65537 for the SN74V283, and
D = 131073 for the SN74V293.
t
sk2
(see Note B)
2
1
W[D-n+1]
Figure 10. Read Timing (First-Word Fall-Through Mode)