Datasheet

SN74V263, SN74V273, SN74V283, SN74V293 8192 18, 16384 18, 32768 18, 65536 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003
×
×
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32
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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1 1
WCLK
D0–D17
t
ENS
WEN
t
DH
t
DS
t
DS
t
DS
t
DS
t
ENH
W1
W2 W3 W4
W[n+2] W[n+3] W[n+4]
D – 1
+ 1
W
2
D – 1
+ 2
W
2
D – 1
+ 3
W
2
W[D-m-2] W[D-m-1] W[D-m] W[D-m+2] W[D] W[D+1]
t
sk1
(see Note A)
RCLK
REN
Q0–Q17
12 3
t
A
Data in Output Register
W1
t
REF
OR
t
sk2
(see Note B)
t
PAES
PAE
t
HF
HF
t
PAFS
PAF
t
WFF
IR
NOTES: A. t
sk1
is the minimum time between a rising WCLK edge and a rising RCLK edge to ensure that OR goes low after two RCLK cycles + t
REF
. If the time between the rising
edge of WLCK and the rising edge of RCLK is less than t
sk1
, OR
deassertion might be delayed one additional RCLK cycle.
B. t
sk2
is the minimum time between a rising WCLK edge and a rising RCLK edge to ensure that PAE
goes high after one RCLK cycle + t
PAES
. If the time between the
rising edge of WCLK and the rising edge of RCLK is less than t
sk2
, PAE
deassertion might be delayed one additional RCLK cycle.
C. LD
= high, OE = low
D. n = PAE
offset, m = PAF offset, D = maximum FIFO depth
E. If ×18 input or ×18 output bus width is selected, D = 8193 for the SN74V263, D = 16385 for the SN74V273, D = 32769 for the SN74V283, and D = 65537 for the
SN74V293. If both ×9 input and ×9 output bus widths are selected, D = 16385 for the SN74V263, D = 32769 for the SN74V273, D = 65537 for the SN74V283, and
D = 131073 for the SN74V293.
F. First-data-word latency: t
sk1
+ 2* T
RCLK
+ t
REF
12
2
W[D-m+1]
Figure 9. Write-Cycle and First-Data-Word-Latency Timing (FWFT Mode)