Datasheet

SN74V263, SN74V273, SN74V283, SN74V293
8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003
31
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
t
DS
t
OLZ
No Operation
RCLK
REN
EF
OE
WEN
1
2
No Operation
Last Word
t
sk1
(see Note A)
t
ref
t
OLZ
t
OHZ
t
ENH
t
ENS
t
DH
t
ENH
t
ENS
t
DS
t
DH
Last Word
t
ENS
t
ENH
t
CLKH
t
CLKL
t
ENS
t
ENH
t
ENH
t
A
t
ref
t
A
t
ref
t
A
t
OE
WCLK
Q
0–Qn
D0–Dn
D0 D1
D0 D1
t
CLK
t
ENS
NOTES: A. t
sk1
is the minimum time between a rising WCLK edge and a rising RCLK edge to ensure that EF goes high (after one
RCLK cycle + t
ref
). If the time between the rising edge of WCLK and the rising edge of RCLK is less than t
sk1
, EF
deassertion can
be delayed one additional RCLK cycle.
B. LD = high
C. First-data-word latency: t
sk1
+ 1*T
RCLK
+ t
REF
Figure 8. Read-Cycle, Empty-Flag, and First-Data-Word-Latency Timing (Standard Mode)