Datasheet

SN74V263, SN74V273, SN74V283, SN74V293
8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003
30
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
t
ENS
t
ENS
t
DS
t
WFF
t
WFF
t
WFF
Data Read Next Data ReadData In Output Register
t
ENH
t
ENH
t
sk1
(see Note A)
t
sk1
(see Note A)
t
CLKH
WEN
RCLK
REN
WCLK
1
2
1
2
Dx
Dx + 1
FF
t
DS
t
WFF
t
A
t
A
Q0–Qn
D0–Dn
t
DH
t
DH
No Write
t
CLK
t
CLKH
No Write
NOTES: A. t
sk1
is the minimum time between a rising RCLK edge and a rising WCLK edge to ensure that FF goes high (after one
WCLK cycle + t
WFF
). If the time between the rising edge of the RCLK and the rising edge of the WCLK is less than t
sk1
, the FF
deassertion can be delayed one additional WCLK cycle.
B. LD
= high, EF = high
Figure 7. Write-Cycle and Full-Flag Timing (Standard Mode)