Datasheet

SN74V263, SN74V273, SN74V283, SN74V293
8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
BYTE ORDER ON INPUT PORT: D17–D9 D8–D0
A
B Write to FIFO
BYTE ORDER ON OUTPUT PORT: Q17–Q9 Q8–Q0
A
B Read from FIFO
BE IW OW
L L L (a) ×18 INPUT TO ×18 OUTPUT – BIG ENDIAN
Q17–Q9 Q8–Q0
B
A Read from FIFO
BE IW OW
H L L (b) ×18 INPUT TO ×18 OUTPUT – LITTLE ENDIAN
Q17–Q9 Q8–Q0
X
A 1st: Read from FIFO
BE IW OW Q17–Q9 Q8–Q0
L L H X B 2nd: Read from FIFO
(c) ×18 INPUT TO ×9 OUTPUT – BIG ENDIAN
Q17–Q9 Q8–Q0
X
B 1st: Read from FIFO
BE IW OW Q17–Q9 Q8–Q0
H L H X A 2nd: Read from FIFO
(d) ×18 INPUT TO ×9 OUTPUT – LITTLE ENDIAN
BYTE ORDER ON INPUT PORT: D17–D9 D8–D0
X
A 1st: Write to FIFO
D17–D9 D8–D0
X B 2nd: Write to FIFO
BYTE ORDER ON OUTPUT PORT: Q17–Q9 Q8–Q0
A
B Read from FIFO
BE IW OW
L H L (a) ×9 INPUT TO ×18 OUTPUT – BIG ENDIAN
Q17–Q9 Q8–Q0
B
A Read from FIFO
BE IW OW
H H L (a) ×9 INPUT TO ×18 OUTPUT – LITTLE ENDIAN
Figure 4. Bus-Matching Byte Arrangement