Datasheet

SN74V263, SN74V273, SN74V283, SN74V293
8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
parallel programming mode (continued)
Writing offsets in parallel employs a dedicated write offset register pointer. Reading offsets employs a dedicated
read offset register pointer. The two pointers operate independently; however, a read and a write should not be
performed simultaneously to the offset registers. A master reset initializes both pointers to the empty offset
(LSB) register. A partial reset has no effect on the position of these pointers (see Figure 3 for a diagram of the
data input lines D0–Dn used during parallel programming).
Write operations to the FIFO are allowed before and during the parallel programming sequence. In this case,
the programming of all offset registers need not occur at one time. One, two, or more offset registers can be
written. Then, by bringing LD
high, write operations can be redirected to the FIFO memory. When LD is set low
again and WEN
is low, the next offset register in sequence is written to. As an alternative to holding WEN low
and switching LD
, parallel programming also can be interrupted by setting LD low and switching WEN.
Note that the status of a programmable-flag (PAE
or PAF) output is invalid during the programming process.
From the time parallel programming has begun, a programmable-flag output is not valid until the appropriate
offset word has been written to the register(s) pertaining to that flag. Measuring from the rising WCLK edge that
achieves the previous criteria, PAF
is valid after two more rising WCLK edges + t
PAF
, and PAE is valid after the
next two rising RCLK edges + t
PAE
+ t
sk2
in synchronous timing mode.
Reading the offset registers employs a dedicated read offset register pointer. The contents of the offset registers
can be read on the Q0–Qn pins when LD
is set low and REN is set low. If the FIFO is configured for both an
input bus width and output bus width set to ×9, the total number of read operations required to read the offset
registers is four for the SN74V263, SN74V273, and SN74V283, or six for the SN74V293 (see Figure 3 for a
diagram of the data input lines D0–Dn used during parallel programming). If the FIFO is configured for an
input-to-output bus width of ×9 to ×18, ×18 to ×9, or ×18 to ×18, the following number of read operations are
required. For an output bus width of ×18, a total of two read operations is required to read the offset registers
for the SN74V263, SN74V273, SN74V283, and SN74V293. For an output bus width of ×9, a total of four read
operations is required to read the offset registers for the SN74V263, SN74V273, SN74V283, and SN74V293
(see Figure 3 ). For example, reading PAE
and PAF on the SN74V293 configured for ×18 bus width proceeds
as follows. Data are read via Qn from the empty offset register on the first and second low-to-high transition of
RCLK. On the third and fourth low-to-high transitions of RCLK, data are read from the full offset register. The
fifth and sixth transition of RCLK reads again from the empty offset register. Note that for a ×9 bus width, one
additional read cycle is required for both the empty offset register and full offset register.
See Figure 17 for timing information.
It is permissible to interrupt the offset register read sequence with reads or writes to the FIFO. The interruption
is accomplished by deasserting REN
, LD, or both together. When REN and LD are restored to a low level,
reading of the offset registers continues where it left off. It should be noted (and care should be taken from the
fact) that when a parallel read of the flag offsets is performed, the data word that was present on the output lines
Qn is overwritten.
Parallel reading of the offset registers always is permitted, regardless of which timing mode (FWFT or standard)
has been selected.