Datasheet

SN74V263, SN74V273, SN74V283, SN74V293
8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1st Parallel Offset Write/Read Cycle 1st Parallel Offset Write/Read Cycle
D/Q8 D/Q0 D/Q8 D/Q0
EMPTY OFFSET REGISTER
EMPTY OFFSET REGISTER
X 8 7 6 5 4 3 2 1 X 8 7 6 5 4 3 2 1
2nd Parallel Offset Write/Read Cycle 2nd Parallel Offset Write/Read Cycle
D/Q8 D/Q0 D/Q8 D/Q0
EMPTY OFFSET REGISTER
EMPTY OFFSET REGISTER
X 16 15 14 13 12 11 10 9 X 16 15 14 13 12 11 10 9
3rd Parallel Offset Write/Read Cycle 3rd Parallel Offset Write/Read Cycle
D/Q8 D/Q0 D/Q8 D/Q0
FULL OFFSET REGISTER
EMPTY OFFSET REGISTER
X 8 7 6 5 4 3 2 1 X X X X X X X X 17
4th Parallel Offset Write/Read Cycle 4th Parallel Offset Write/Read Cycle
D/Q8 D/Q0 D/Q8 D/Q0
FULL OFFSET REGISTER
FULL OFFSET REGISTER
X 16 15 14 13 12 11 10 9 X 8 7 6 5 4 3 2 1
SN74V263/SN74V273/SN74V283/SN74V293
×9 Bus Width (see Note A)
5th Parallel Offset Write/Read Cycle
D/Q8 D/Q0
X = don’t care FULL OFFSET REGISTER
X 16 15 14 13 12 11 10 9
6th Parallel Offset Write/Read Cycle
D/Q8 D/Q0
FULL OFFSET REGISTER
X X X X X X X X 17
SN74V293
×9 Bus Width (see Note A)
×9 TO ×9 MODE ALL OTHER MODES
Number of bits used:
14 bits for the SN74V263
15 bits for the SN74V273
16 bits for the SN74V283
17 bits for the SN74V293
Note: All unused bits of the
LSB and MSB are don’t care
Number of bits used:
13 bits for the SN74V263
14 bits for the SN74V273
15 bits for the SN74V283
16 bits for the SN74V293
Note: All unused bits of the
LSB and MSB are don’t care
NOTE A: When programming the SN74V293 with an input bus width of ×9 and output bus width of ×18, four write cycles are required. When
reading the SN74V293 with an output bus width of ×9 and input bus width of ×18, four read cycles are required. A total of six program/read
cycles are required for ×9 bus width if both the input and output bus widths are set to ×9.
Figure 3. Programmable Flag Offset Programming Sequence