Datasheet

SN74V263, SN74V273, SN74V283, SN74V293
8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Table 2. Default Programmable Flag Offsets
OFFSETS (n, m)
†
OFFSETS (n, m)
†
LD
FSEL0
FSEL1
SN74V263
LD
FSEL0
FSEL1
SN74V283
LD
FSEL0
FSEL1
SN74V263
SN74V273
LD
FSEL0
FSEL1
ALL OTHER
MODES
×9 TO ×9
MODE
SN74V293
H L L 1,023 L L H 511 16383 16383
L L H 511 L H L 255 8191 8191
L H L 255 L H H 63 4,095 4,095
L L L 127 H L H 31 2,047 2,047
L H H 63 H L L 1,023 1,023 1,023
H L H 31 H H L 15 511 511
H H L 15 H H H 7 255 255
H H H 7 L L L 127 127 127
†
n = empty offset for PAE
, m = full offset for PAF
programming flag offsets
Full and empty flag offset values are user programmable. The SN74V263, SN74V273, SN74V283, and
SN74V293 have internal registers for these offsets. Eight default offset values are selectable during master
reset. These offset values are shown in Table 2. Offset values also can be programmed into the FIFO by serial
or parallel loading. The loading method is selected using LD
. During master reset, the state of the LD input
determines whether serial or parallel flag offset programming is enabled. A high on LD
during master reset
selects serial loading of offset values. A low on LD
during master reset selects parallel loading of offset values.
In addition to loading offset values into the FIFO, it also is possible to read the current offset values. Offset values
can be read via the parallel output ports Q0–Qn, regardless of the programming mode selected (serial or
parallel). It is not possible to read the offset values in serial fashion.
Figure 3 summarizes the control pins and sequence for both serial and parallel programming modes. A more
detailed description is given in the following paragraphs.
The offset registers can be programmed (and reprogrammed) any time after master reset, regardless of whether
serial or parallel programming has been selected. Valid programming ranges are from 0 to D – 1.
synchronous vs asynchronous programmable-flag timing selection
The SN74V263, SN74V273, SN74V283, and SN74V293 can be configured during the master reset cycle with
either synchronous or asynchronous timing for PAF
and PAE flags by use of the PFM pin.
If synchronous PAF
/PAE configuration is selected (PFM high during MRS), PAF is asserted and updated on the
rising edge of WCLK only and not RCLK. Similarly, PAE
is asserted and updated on the rising edge of RCLK
only and not WCLK (see Figure 18 for synchronous PAF
timing and Figure 19 for synchronous PAE timing).
If asynchronous PAF
/PAE configuration is selected (PFM low during MRS), PAF is asserted low on the
low-to-high transition of WCLK and PAF
is reset to high on the low-to-high transition of RCLK. Similarly, PAE
is asserted low on the low-to-high transition of RCLK. PAE is reset to high on the low-to-high transition of WCLK
(see Figure 20 for asynchronous PAF
timing and Figure 21 for asynchronous PAE timing).