Datasheet

SN74V263, SN74V273, SN74V283, SN74V293
8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
empty flag/output ready (EF/OR)
EF
/OR is a dual-purpose pin. In FWFT mode, the OR function is selected. OR goes low at the same time that
the first word written to an empty FIFO appears valid on the outputs. OR
stays low after the RCLK low-to-high
transition that shifts the last word from the FIFO memory to the outputs. OR
goes high only with a true read
(RCLK with REN
= low). The previous data stays at the outputs, indicating the last word was read. Further data
reads are inhibited until OR
goes low again.
See Figure 10 for timing information.
In the standard mode, the EF
function is selected. When the FIFO is empty, EF goes low, inhibiting further read
operations. When EF
is high, the FIFO is not empty.
See Figure 8 for timing information.
EF
/OR is synchronous and updated on the rising edge of RCLK.
In FWFT mode, OR
is a triple register-buffered output. In standard mode, EF is a double register-buffered
output.
programmable almost-full flag (PAF
)
PAF
goes low when the FIFO reaches the almost-full condition. In FWFT mode, if ×18 input or ×18 output bus
width is selected, PAF
goes low after (8193 – m) writes for the SN74V263, (16385 – m) writes for the SN74V273,
(32769 – m) writes for the SN74V283, and (65537 – m) writes for the SN74V293. If both ×9 input and ×9 output
bus widths are selected, PAF
goes low after (16385 – m) writes for the SN74V263, (32769 – m) writes for the
SN74V273, (65537 – m) writes for the SN74V283, and (131073 – m) writes for the SN74V293. The offset m
is the full offset value. The default setting for this value is shown in Table 2.
In standard mode, if no reads are performed after MRS, PAF goes low after (D – m) words are written to the
FIFO. If ×18 input or ×18 output bus width is selected, (D – m) = (8192 – m) writes for the SN74V263, (16384 – m)
writes for the SN74V273, (32768 – m) writes for the SN74V283, and (65536 – m) writes for the SN74V293. If
both ×9 input and ×9 output bus widths are selected, (D – m) = (16384 – m) writes for the SN74V263,
(32768 – m) writes for the SN74V273, (65536 – m) writes for the SN74V283, and (131072 – m) writes for the
SN74V293. The offset m is the full offset value. The default setting for this value is shown in Table 2.
See Figure 18 for timing information.
If asynchronous PAF
configuration is selected, the PAF is asserted low on the low-to-high transition of WCLK.
PAF
is reset to high on the low-to-high transition of RCLK. If synchronous PAF configuration is selected, the PAF
is updated on the rising edge of WCLK (see Figure 20).
programmable almost-empty flag (PAE
)
PAE
goes low when the FIFO reaches the almost-empty condition. In FWFT mode, PAE goes low when there
are n + 1 words, or fewer, in the FIFO. The default setting for this value is shown in Table 2.
In standard mode, PAE
goes low when there are n words, or fewer, in the FIFO. The offset n is the empty offset
value. The default setting for this value is shown in Table 2.
See Figure 19 for timing information.
If asynchronous PAE
configuration is selected, PAE is asserted low on the low-to-high transition of the read clock
(RCLK). PAE
is reset to high on the low-to-high transition of the write clock (WCLK). If synchronous PAE
configuration is selected, PAE is updated on the rising edge of RCLK.
See Figure 21 for timing information.