Datasheet

SN74V263, SN74V273, SN74V283, SN74V293
8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18
3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES
SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
programmable-flag mode (PFM)
During master reset, a low on PFM selects asynchronous programmable-flag timing mode. A high on PFM
selects synchronous programmable-flag timing mode. If asynchronous PAF
/PAE configuration is selected
(PFM low during MRS
), PAE is asserted low on the low-to-high transition of RCLK. PAE is reset to high on the
low-to-high transition of WCLK. Similarly, PAF
is asserted low on the low-to-high transition of WCLK, and PAF
is reset to high on the low-to-high transition of RCLK.
If the synchronous PAE
/PAF configuration is selected (PFM high during MRS), PAE is asserted and updated
on the rising edge of RCLK only, and not WCLK. Similarly, PAF
is asserted and updated on the rising edge of
WCLK only, and not RCLK. The mode desired is configured during master reset by the state of PFM.
interspersed parity (IP)
During master reset, a low on IP selects noninterspersed-parity mode. A high selects interspersed-parity mode.
The IP bit function allows the user to select the parity bit in the word loaded into the parallel port (D0–Dn) when
programming the flag offsets. If interspersed-parity mode is selected, the FIFO assumes that the parity bit is
located in bit positions D8 and D17 during the parallel programming of the flag offsets and, therefore, ignores
D8 when loading the offset register in parallel mode. This also is applied to the output register when reading
the value of the offset register. If interspersed parity is selected, output Q8 is invalid. If noninterspersed-parity
mode is selected, D16 and D17 are the parity bits and are ignored during parallel programming of the offsets
(D8 becomes a valid bit). Additionally, output Q8 becomes a valid bit when performing a read of the offset
register. Interspersed-parity mode is selected during master reset by state of IP.
outputs
full flag/input ready (FF
/IR)
FI
/IR is a dual-purpose pin. In FWFT mode, the IR function is selected. IR goes low when memory space is
available for writing in data. When there is no longer any free space left, IR
goes high, inhibiting further write
operations. If no reads are performed after a reset (either MRS
or PRS), IR goes high after D writes to the FIFO.
If ×18 input or ×18 output bus width is selected, D = 8193 for the SN74V263, D = 16385 for the SN74V273,
D = 32769 for the SN74V283, and D = 65537 for the SN74V293. If both ×9 input and ×9 output bus widths are
selected, D = 16385 for the SN74V263, D = 32769 for the SN74V273, D = 65537 for the SN74V283, and
D = 131073 for the SN74V293.
See Figure 9 for timing information.
In standard mode, the FF
function is selected. When the FIFO is full, FF goes low, inhibiting further write
operations. When FF
is high, the FIFO is not full. If no reads are performed after a reset (either MRS or PRS),
FF
goes low after D writes to the FIFO. If ×18 input or ×18 output bus width is selected, D = 8192 for the
SN74V263, D = 16384 for the SN74V273, D = 32768 for the SN74V283, and D = 65536 for the SN74V293. If
both ×9 input and ×9 output bus widths are selected, D = 16384 for the SN74V263, D = 32768 for the SN74V273,
D = 65536 for the SN74V283, and D = 131072 for the SN74V293.
See Figure 7 for timing information.
The IR
status not only measures the contents of the FIFO memory, but also counts the presence of a word in
the output register. Thus, in FWFT mode, the total number of writes necessary to deassert IR
is one greater than
needed to assert FF
in standard mode.
FF
/IR is synchronous and updated on the rising edge of WCLK. FF/IR are double register-buffered outputs.